Home
last modified time | relevance | path

Searched refs:rcc_base (Results 1 – 9 of 9) sorted by relevance

/rk3399_ARM-atf/drivers/st/reset/
H A Dstm32mp1_reset.c33 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp_reset_assert() local
35 mmio_write_32(rcc_base + offset, bitmsk); in stm32mp_reset_assert()
40 while ((mmio_read_32(rcc_base + offset) & bitmsk) == 0U) { in stm32mp_reset_assert()
54 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp_reset_deassert() local
56 mmio_write_32(rcc_base + offset, bitmsk); in stm32mp_reset_deassert()
61 while ((mmio_read_32(rcc_base + offset) & bitmsk) != 0U) { in stm32mp_reset_deassert()
73 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp_system_reset() local
75 mmio_setbits_32(rcc_base + RCC_MP_GRSTCSETR, in stm32mp_system_reset()
H A Dstm32mp2_reset.c33 uintptr_t rcc_base = stm32mp_rcc_base(); in reset_toggle() local
36 mmio_setbits_32(rcc_base + offset, bitmsk); in reset_toggle()
39 mmio_clrbits_32(rcc_base + offset, bitmsk); in reset_toggle()
46 while ((mmio_read_32(rcc_base + offset) & bitmsk) != bit_check) { in reset_toggle()
68 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp_system_reset() local
70 mmio_setbits_32(rcc_base + RCC_GRSTCSETR, RCC_GRSTCSETR_SYSRST); in stm32mp_system_reset()
/rk3399_ARM-atf/drivers/st/ddr/
H A Dstm32mp2_ddr_helpers.c254 uintptr_t rcc_base = stm32mp_rcc_base(); in sr_ssr_entry() local
288 mmio_clrsetbits_32(rcc_base + RCC_DDRCPCFGR, RCC_DDRCPCFGR_DDRCPLPEN, in sr_ssr_entry()
290 mmio_setbits_32(rcc_base + RCC_DDRPHYCCFGR, RCC_DDRPHYCCFGR_DDRPHYCEN); in sr_ssr_entry()
291 mmio_setbits_32(rcc_base + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRPHYDLP); in sr_ssr_entry()
299 uintptr_t rcc_base = stm32mp_rcc_base(); in sr_ssr_exit() local
301 mmio_setbits_32(rcc_base + RCC_DDRCPCFGR, in sr_ssr_exit()
303 mmio_clrbits_32(rcc_base + RCC_DDRITFCFGR, RCC_DDRITFCFGR_DDRPHYDLP); in sr_ssr_exit()
304 mmio_setbits_32(rcc_base + RCC_DDRPHYCCFGR, RCC_DDRPHYCCFGR_DDRPHYCEN); in sr_ssr_exit()
504 uintptr_t rcc_base = stm32mp_rcc_base(); in ddr_sub_system_clk_off() local
510 mmio_write_32(rcc_base + RCC_DDRCPCFGR, RCC_DDRCPCFGR_DDRCPRST); in ddr_sub_system_clk_off()
[all …]
/rk3399_ARM-atf/drivers/st/clk/
H A Dstm32mp1_clk.c931 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_rcc_is_secure() local
934 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; in stm32mp1_rcc_is_secure()
939 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_rcc_is_mckprot() local
942 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; in stm32mp1_rcc_is_mckprot()
996 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_clk_get_parent() local
1023 p_sel = (mmio_read_32(rcc_base + sel->offset) & in stm32mp1_clk_get_parent()
1050 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_pll_get_fvco() local
1052 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); in stm32mp1_pll_get_fvco()
1053 fracr = mmio_read_32(rcc_base + pll->pllxfracr); in stm32mp1_pll_get_fvco()
1105 uintptr_t rcc_base = stm32mp_rcc_base(); in get_clock_rate() local
[all …]
H A Dclk-stm32mp2.c44 uintptr_t rcc_base; member
981 uintptr_t rcc_base = priv->base; in clk_flexgen_recalc() local
986 prediv = mmio_read_32(rcc_base + RCC_PREDIV0CFGR + (0x4U * channel)) & in clk_flexgen_recalc()
988 findiv = mmio_read_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel)) & in clk_flexgen_recalc()
1020 uintptr_t rcc_base = priv->base; in clk_flexgen_get_parent() local
1024 sel = mmio_read_32(rcc_base + address) & RCC_XBARxCFGR_XBARxSEL_MASK; in clk_flexgen_get_parent()
1033 uintptr_t rcc_base = priv->base; in clk_flexgen_gate_enable() local
1036 mmio_setbits_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel), in clk_flexgen_gate_enable()
1046 uintptr_t rcc_base = priv->base; in clk_flexgen_gate_disable() local
1049 mmio_clrbits_32(rcc_base + RCC_FINDIV0CFGR + (0x4U * channel), in clk_flexgen_gate_disable()
[all …]
H A Dclk-stm32-core.c917 uintptr_t rcc_base = priv->base; in timer_recalc_rate() local
919 prescaler = mmio_read_32(rcc_base + cfg->apbdiv) & in timer_recalc_rate()
922 timpre = mmio_read_32(rcc_base + cfg->timpre) & in timer_recalc_rate()
H A Dclk-stm32mp13.c967 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_set_hsidiv() local
968 uintptr_t address = rcc_base + RCC_OCRDYR; in stm32mp1_set_hsidiv()
970 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, in stm32mp1_set_hsidiv()
/rk3399_ARM-atf/plat/st/stm32mp1/
H A Dbl2_plat_setup.c212 uintptr_t rcc_base; in bl2_el3_plat_arch_setup() local
234 rcc_base = stm32mp_rcc_base(); in bl2_el3_plat_arch_setup()
248 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { in bl2_el3_plat_arch_setup()
249 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); in bl2_el3_plat_arch_setup()
251 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == in bl2_el3_plat_arch_setup()
256 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); in bl2_el3_plat_arch_setup()
264 mmio_clrsetbits_32(rcc_base + RCC_RDLSICR, in bl2_el3_plat_arch_setup()
/rk3399_ARM-atf/plat/st/stm32mp2/
H A Dbl2_plat_setup.c116 uintptr_t rcc_base = stm32mp_rcc_base(); in reset_backup_domain() local
138 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCCKEN) == 0U) { in reset_backup_domain()
139 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); in reset_backup_domain()
141 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 0U) { in reset_backup_domain()
145 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); in reset_backup_domain()