Lines Matching refs:rcc_base
931 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_rcc_is_secure() local
934 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; in stm32mp1_rcc_is_secure()
939 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_rcc_is_mckprot() local
942 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; in stm32mp1_rcc_is_mckprot()
996 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_clk_get_parent() local
1023 p_sel = (mmio_read_32(rcc_base + sel->offset) & in stm32mp1_clk_get_parent()
1050 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_pll_get_fvco() local
1052 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); in stm32mp1_pll_get_fvco()
1053 fracr = mmio_read_32(rcc_base + pll->pllxfracr); in stm32mp1_pll_get_fvco()
1105 uintptr_t rcc_base = stm32mp_rcc_base(); in get_clock_rate() local
1110 reg = mmio_read_32(rcc_base + RCC_MPCKSELR); in get_clock_rate()
1124 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR); in get_clock_rate()
1138 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR); in get_clock_rate()
1154 reg = mmio_read_32(rcc_base + RCC_AXIDIVR); in get_clock_rate()
1159 reg = mmio_read_32(rcc_base + RCC_APB4DIVR); in get_clock_rate()
1163 reg = mmio_read_32(rcc_base + RCC_APB5DIVR); in get_clock_rate()
1175 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR); in get_clock_rate()
1194 reg = mmio_read_32(rcc_base + RCC_MCUDIVR); in get_clock_rate()
1199 reg = mmio_read_32(rcc_base + RCC_APB1DIVR); in get_clock_rate()
1203 reg = mmio_read_32(rcc_base + RCC_APB2DIVR); in get_clock_rate()
1207 reg = mmio_read_32(rcc_base + RCC_APB3DIVR); in get_clock_rate()
1216 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR); in get_clock_rate()
1248 clock /= (mmio_read_32(rcc_base + RCC_RTCDIVR) & RCC_DIVR_DIV_MASK) + 1U; in get_clock_rate()
1306 uintptr_t rcc_base = stm32mp_rcc_base(); in __clk_enable() local
1311 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit)); in __clk_enable()
1313 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit)); in __clk_enable()
1319 uintptr_t rcc_base = stm32mp_rcc_base(); in __clk_disable() local
1324 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET, in __clk_disable()
1327 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit)); in __clk_disable()
1333 uintptr_t rcc_base = stm32mp_rcc_base(); in __clk_is_enabled() local
1335 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit); in __clk_is_enabled()
1485 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp_clk_get_rate() local
1506 prescaler = mmio_read_32(rcc_base + RCC_APB1DIVR) & in stm32mp_clk_get_rate()
1508 timpre = mmio_read_32(rcc_base + RCC_TIMG1PRER) & in stm32mp_clk_get_rate()
1517 prescaler = mmio_read_32(rcc_base + RCC_APB2DIVR) & in stm32mp_clk_get_rate()
1519 timpre = mmio_read_32(rcc_base + RCC_TIMG2PRER) & in stm32mp_clk_get_rate()
1580 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_lse_enable() local
1583 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) { in stm32mp1_lse_enable()
1588 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); in stm32mp1_lse_enable()
1592 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); in stm32mp1_lse_enable()
1599 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> in stm32mp1_lse_enable()
1609 mmio_clrsetbits_32(rcc_base + RCC_BDCR, in stm32mp1_lse_enable()
1635 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_hse_enable() local
1638 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP); in stm32mp1_hse_enable()
1642 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP); in stm32mp1_hse_enable()
1651 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON); in stm32mp1_hse_enable()
1655 if ((mmio_read_32(rcc_base + RCC_OCENSETR) & RCC_OCENR_HSEBYP) && in stm32mp1_hse_enable()
1681 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_set_hsidiv() local
1682 uintptr_t address = rcc_base + RCC_OCRDYR; in stm32mp1_set_hsidiv()
1684 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, in stm32mp1_set_hsidiv()
1730 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_check_pll_conf() local
1731 uintptr_t pllxcr = rcc_base + pll->pllxcr; in stm32mp1_check_pll_conf()
1733 uintptr_t clksrc_address = rcc_base + (clksrc >> 4); in stm32mp1_check_pll_conf()
1750 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK; in stm32mp1_check_pll_conf()
1770 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) { in stm32mp1_check_pll_conf()
1777 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) { in stm32mp1_check_pll_conf()
1788 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) { in stm32mp1_check_pll_conf()
1858 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_pll_config_output() local
1867 mmio_write_32(rcc_base + pll->pllxcfgr2, value); in stm32mp1_pll_config_output()
1874 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_pll_config() local
1880 src = mmio_read_32(rcc_base + pll->rckxselr) & in stm32mp1_pll_config()
1901 mmio_write_32(rcc_base + pll->pllxcfgr1, value); in stm32mp1_pll_config()
1905 mmio_write_32(rcc_base + pll->pllxfracr, value); in stm32mp1_pll_config()
1908 mmio_write_32(rcc_base + pll->pllxfracr, value); in stm32mp1_pll_config()
1911 mmio_write_32(rcc_base + pll->pllxfracr, value); in stm32mp1_pll_config()
2435 uintptr_t rcc_base = stm32mp_rcc_base(); in get_parent_id_parent() local
2482 p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) & in get_parent_id_parent()
2491 p_sel = mmio_read_32(rcc_base + pll->rckxselr) & in get_parent_id_parent()
2587 uintptr_t rcc_base = stm32mp_rcc_base(); in stm32mp1_clk_mcuss_protect() local
2590 mmio_setbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); in stm32mp1_clk_mcuss_protect()
2592 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); in stm32mp1_clk_mcuss_protect()