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Searched refs:r1 (Results 1 – 25 of 66) sorted by relevance

123

/rk3399_ARM-atf/lib/xlat_tables_v2/aarch32/
H A Denable_mmu.S18 ldcopr r1, SCTLR
19 tst r1, #SCTLR_M_BIT
30 ldr r1, [r0, #(MMU_CFG_MAIR << 3)]
31 stcopr r1, MAIR0
38 ldr r1, [r0, #(MMU_CFG_TTBR0 << 3)]
40 stcopr16 r1, r2, TTBR0_64
43 mov r1, #0
45 stcopr16 r1, r2, TTBR1_64
56 ldcopr r1, SCTLR
58 orr r1, r1, r2
[all …]
/rk3399_ARM-atf/lib/libc/aarch32/
H A Dmemset.S29 strbhs r1, [r12], #1
35 aligned:bfi r1, r1, #8, #8 /* propagate 'val' */
36 bfi r1, r1, #16, #16
38 mov r3, r1
44 mov r4, r1
45 mov lr, r1
49 stmiahs r12!, {r1, r3, r4, lr}
50 stmiahs r12!, {r1, r3, r4, lr}
54 stmiacs r12!, {r1, r3, r4, lr} /* write 16 bytes */
56 stmiami r12!, {r1, r3} /* write 8 bytes */
[all …]
/rk3399_ARM-atf/drivers/arm/pl011/aarch32/
H A Dpl011_console.S46 cmp r1, #0
56 lsl r1, r1, #2
59 softudiv r0,r1,r2,r3
63 udiv r2, r1, r2
66 lsr r1, r2, #6
68 str r1, [r0, #UARTIBRD]
70 and r1, r2, #0x3f
72 str r1, [r0, #UARTFBRD]
73 mov r1, #PL011_LINE_CONTROL
74 str r1, [r0, #UARTLCR_H]
[all …]
/rk3399_ARM-atf/include/arch/aarch32/
H A Dconsole_macros.S26 ldr r1, =console_\_driver\()_putc
28 mov r1, #0
30 str r1, [r0, #CONSOLE_T_PUTC]
38 ldr r1, =console_\_driver\()_getc
39 str r1, [r0, #CONSOLE_T_GETC]
42 mov r1, #0
43 str r1, [r0, #CONSOLE_T_GETC]
48 ldr r1, =console_\_driver\()_flush
50 mov r1, #0
52 str r1, [r0, #CONSOLE_T_FLUSH]
[all …]
H A Del3_common_macros.S33 ldr r1, =(SCTLR_I_BIT | SCTLR_A_BIT)
35 orr r0, r0, r1
77 ldcopr r1, ID_DFR0
78 ubfx r1, r1, #ID_DFR0_COPTRC_SHIFT, #ID_DFR0_COPTRC_LENGTH
79 cmp r1, #COPTRC_IMPLEMENTED
144 ldcopr r1, ID_DFR0
145 ubfx r1, r1, #ID_DFR0_TRACEFILT_SHIFT, #ID_DFR0_TRACEFILT_LENGTH
146 cmp r1, #TRACEFILT_IMPLEMENTED
306 ldr r1, =PAGE_START_MASK
307 and r0, r0, r1
[all …]
H A Dsmccc_macros.S135 ldr r1, [r0, #SMC_CTX_SCR]
136 stcopr r1, SCR
142 tst r1, #SCR_NS_BIT
154 ldcopr r1, SDCR
155 tst r1, #SDCR_SCCD_BIT
161 ldr r1, [r0, #SMC_CTX_PMCR]
162 stcopr r1, PMCR
165 add r1, r0, #SMC_CTX_SP_USR
175 ldm r1!, {sp, lr}
178 ldm r1!, {r2, sp, lr}
[all …]
/rk3399_ARM-atf/lib/cpus/aarch32/
H A Dcortex_a57.S19 ldcopr16 r0, r1, CORTEX_A57_ECTLR
20 bic64_imm r0, r1, CORTEX_A57_ECTLR_SMP_BIT
21 stcopr16 r0, r1, CORTEX_A57_ECTLR
31 ldcopr16 r0, r1, CORTEX_A57_ECTLR
32 orr64_imm r0, r1, CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT
33 bic64_imm r0, r1, (CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK | \
35 stcopr16 r0, r1, CORTEX_A57_ECTLR
77 ldcopr16 r0, r1, CORTEX_A57_CPUACTLR
78 orr64_imm r0, r1, CORTEX_A57_CPUACTLR_NO_ALLOC_WBWA
79 stcopr16 r0, r1, CORTEX_A57_CPUACTLR
[all …]
H A Dcortex_a72.S18 ldcopr16 r0, r1, CORTEX_A72_ECTLR
19 orr64_imm r0, r1, CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT
20 bic64_imm r0, r1, (CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK | \
22 stcopr16 r0, r1, CORTEX_A72_ECTLR
32 ldcopr16 r0, r1, CORTEX_A72_CPUACTLR
33 orr64_imm r0, r1, CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH
34 stcopr16 r0, r1, CORTEX_A72_CPUACTLR
46 ldcopr16 r0, r1, CORTEX_A72_ECTLR
47 bic64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT
48 stcopr16 r0, r1, CORTEX_A72_ECTLR
[all …]
H A Dcpu_helpers.S45 ldr r1, [r4], #CPU_OPS_SIZE
46 and r1, r1, r3
49 cmp r1, r2
87 ldr r1, [r0, #CPU_RESET_FUNC]
88 cmp r1, #0
90 bxne r1
110 ldcopr r1, MIDR
119 ubfx r0, r1, #(MIDR_VAR_SHIFT - MIDR_REV_BITS), #(MIDR_REV_BITS + MIDR_VAR_BITS)
120 bfi r0, r1, #MIDR_REV_SHIFT, #MIDR_REV_BITS
131 cmp r0, r1
[all …]
H A Dcortex_a53.S24 ldcopr16 r0, r1, CORTEX_A53_ECTLR
25 bic64_imm r0, r1, CORTEX_A53_ECTLR_SMP_BIT
26 stcopr16 r0, r1, CORTEX_A53_ECTLR
92 mov r1, #0x02
141 ldcopr16 r0, r1, CORTEX_A53_CPUACTLR
142 orr64_imm r0, r1, CORTEX_A53_CPUACTLR_DTAH
143 stcopr16 r0, r1, CORTEX_A53_CPUACTLR
149 mov r1, #0x03
178 ldcopr16 r0, r1, CORTEX_A53_CPUACTLR
179 orr64_imm r0, r1, CORTEX_A53_CPUACTLR_ENDCCASCI
[all …]
/rk3399_ARM-atf/lib/aarch32/
H A Dmisc_helpers.S51 length .req r1 /* Length in bytes of the region to zero out */
56 stop_address .req r1 /* Address past the last zeroed byte */
147 orr r3, r0, r1
155 ldr r3, [r1], #4
163 ldrb r3, [r1], #1
176 mov r1, #(SCTLR_M_BIT | SCTLR_C_BIT)
183 bic r0, r0, r1
192 ldr r1, =(SCTLR_M_BIT | SCTLR_C_BIT | SCTLR_I_BIT)
219 mov r7, r1
223 orr r0, r0, r1
[all …]
/rk3399_ARM-atf/plat/qti/msm8916/aarch32/
H A Dmsm8916_helpers.S38 ldr r1, =BLSP_UART_BASE
52 ldr r1, =BLSP_UART_BASE
64 ldr r1, =BLSP_UART_BASE
76 mov r1, #0
77 str r1, [r0]
88 ldcopr r1, MPIDR
89 and r0, r1, #MPIDR_CPU_MASK
91 and r1, r1, #MPIDR_CLUSTER_MASK
92 orr r0, r0, r1, LSR #(MPIDR_AFFINITY_BITS - \
119 ldr r1, =APCS_CFG(0)
[all …]
H A Duartdm_console.S49 str r1, [r0, #CONSOLE_T_BASE]
76 ldr r3, [r1, #UART_DM_SR]
85 str r3, [r1, #UART_DM_CR]
89 str r3, [r1, #UART_DM_CR]
98 str r3, [r1, #UART_DM_DMEN]
102 str r3, [r1, #UART_DM_CR]
117 ldr r1, [r1, #CONSOLE_T_BASE]
135 ldr r2, [r1, #UART_DM_SR]
141 str r2, [r1, #UART_DM_TF]
144 ldr r2, [r1, #UART_DM_SR]
[all …]
/rk3399_ARM-atf/drivers/st/uart/aarch32/
H A Dstm32_console.S51 cmp r1, #0
61 cmp r1, #0
77 add r3, r1, r3
84 add r3, r3, r1, lsl #1
86 and r1, r3, #USART_BRR_DIV_FRACTION
87 lsr r1, r1, #1
89 orr r3, r3, r1
90 ldr r1, [r0, #USART_CR1]
91 orr r1, r1, #USART_CR1_OVER8
92 str r1, [r0, #USART_CR1]
[all …]
/rk3399_ARM-atf/lib/psci/aarch32/
H A Dpsci_helpers.S27 ldcopr r1, SCTLR
28 bic r1, #SCTLR_C_BIT
29 stcopr r1, SCTLR
38 mov r1, sp
39 sub r1, r0, r1
50 sub r1, sp, r0
83 mov r1, sp
84 sub r1, r0, r1
/rk3399_ARM-atf/plat/st/stm32mp1/
H A Dstm32mp1_helper.S171 ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
172 and r0, r1
186 and r1, r0, #MPIDR_CPU_MASK
188 add r0, r1, r0, LSR #6
209 ldr r1, =(RCC_BASE + DEBUG_UART_RST_REG)
211 str r2, [r1]
213 ldr r0, [r1]
216 str r2, [r1, #4] /* RSTCLR register */
218 ldr r0, [r1]
222 ldr r1, =(RCC_BASE + DEBUG_UART_TX_GPIO_BANK_CLK_REG)
[all …]
/rk3399_ARM-atf/bl2/aarch32/
H A Dbl2_entrypoint.S33 mov r9, r1
72 ldr r1, =__RW_END__
73 sub r1, r1, r0
83 ldr r1, =__BSS_END__
84 sub r1, r1, r0
89 ldr r1, =__COHERENT_RAM_END_UNALIGNED__
90 sub r1, r1, r0
118 mov r1, r9
/rk3399_ARM-atf/drivers/ti/uart/aarch32/
H A D16550_console.S45 cmp r1, #0
53 udiv r2, r1, r2
54 and r1, r2, #0xff /* w1 = DLL */
60 str r1, [r0, #UARTDLL] /* program DLL */
117 cmp r1, #0
145 cmp r1, #0
153 1: ldr r2, [r1, #UARTLSR]
158 str r2, [r1, #UARTTX]
161 2: ldr r2, [r1, #UARTLSR]
165 str r0, [r1, #UARTTX]
[all …]
/rk3399_ARM-atf/plat/qemu/common/aarch32/
H A Dplat_helpers.S34 and r1, r0, #MPIDR_CPU_MASK
36 add r0, r1, r0, LSR #6
49 ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
50 and r0, r1
74 ldr r1, [r2, r0]
75 cmp r1, #PLAT_QEMU_HOLD_STATE_WAIT
79 mov r1, #PLAT_QEMU_HOLD_STATE_WAIT
80 str r1, [r2, r0]
84 ldr r1, [r0]
85 bx r1
[all …]
/rk3399_ARM-atf/plat/arm/css/common/aarch32/
H A Dcss_helpers.S58 and r1, r0, #MPIDR_CPU_MASK
61 add r0, r1, r0, LSR #6
79 mov r1, #0xffffffff
80 cmp r0, r1
93 ldr r1, =SCP_BOOT_CFG_ADDR
94 ldr r1, [r1]
95 ubfx r1, r1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \
97 cmp r0, r1
/rk3399_ARM-atf/plat/arm/board/a5ds/aarch32/
H A Da5ds_helpers.S36 ldr r1, [r2, r0]
37 cmp r1, #A5DS_HOLD_STATE_WAIT
40 ldr r1, [r0]
41 bx r1
71 ldr r1, =MPIDR_AFFINITY_MASK
72 and r0, r1
116 ubfx r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
121 mla r1, r2, r3, r1
123 mla r0, r1, r3, r0
/rk3399_ARM-atf/bl2u/aarch32/
H A Dbl2u_entrypoint.S33 mov r11, r1
71 ldr r1, =__RW_END__
72 sub r1, r1, r0
82 ldr r1, =__BSS_END__
83 sub r1, r1, r0
111 mov r1, r10
/rk3399_ARM-atf/bl32/sp_min/aarch32/
H A Dentrypoint.S70 mov r10, r1
118 mov r1, r10
134 ldr r1, =__DATA_END__
135 sub r1, r1, r0
139 ldr r1, =__BSS_END__
140 sub r1, r1, r0
144 ldr r1, =__PER_CPU_END__
145 sub r1, r1, r0
169 strd r0, r1, [sp, #SMC_CTX_GPREG_R0]
170 ldcopr16 r0, r1, CNTPCT_64
[all …]
/rk3399_ARM-atf/plat/arm/board/fvp/aarch32/
H A Dfvp_helpers.S54 ldr r1, =PWRC_BASE
55 str r2, [r1, #PSYSR_OFF]
56 ldr r2, [r1, #PSYSR_OFF]
98 ldr r1, =MPIDR_AFFINITY_MASK
99 and r0, r1
133 ubfx r1, r3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
138 mla r1, r2, r3, r1
140 mla r0, r1, r3, r0
/rk3399_ARM-atf/plat/rockchip/common/aarch32/
H A Dplat_helpers.S39 and r1, r0, #MPIDR_CPU_MASK
45 add r0, r1, r0, LSR #PLAT_RK_CLST_TO_CPUID_SHIFT
67 ldr r1, =(PLAT_RK_MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
69 ldr r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
71 and r0, r1
119 ldr r1, [r4]
124 cmp r1, #PMU_CPU_AUTO_PWRDN
126 cmp r1, #PMU_CPU_HOTPLUG
137 mov r1, #0
138 str r1, [r4]

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