| /rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/topology/default/ |
| H A D | pwr.c | 46 unsigned int pwr_domain_coordination(enum pwr_domain_status pwr, in pwr_domain_coordination() argument
62 if (pwr > PWR_DOMAIN_OFF) in pwr_domain_coordination()
65 if (!IS_MT_PLAT_PWR_STATE_MCUSYS(state->pwr.state_id)) { in pwr_domain_coordination()
67 if (pwr == PWR_DOMAIN_OFF) in pwr_domain_coordination()
78 if (state->pwr.afflv >= PLAT_MT_CPU_SUSPEND_CLUSTER) in pwr_domain_coordination()
84 if (pwr == PWR_DOMAIN_OFF) { in pwr_domain_coordination()
85 if (IS_PLAT_MCUSYSOFF_AFFLV(state->pwr.afflv) && in pwr_domain_coordination()
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| H A D | rules.mk | 11 LOCAL_SRCS-y := ${LOCAL_DIR}/pwr.c
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| /rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/topology/group_4_3_1/ |
| H A D | pwr.c | 60 unsigned int pwr_domain_coordination(enum pwr_domain_status pwr, in pwr_domain_coordination() argument
71 if (state->pwr.afflv >= PLAT_MT_CPU_SUSPEND_CLUSTER) { in pwr_domain_coordination()
80 if ((pwr == PWR_DOMAIN_OFF) || (pwr == PWR_DOMAIN_SMP_OFF)) { in pwr_domain_coordination()
96 if (pwr > PWR_DOMAIN_OFF) in pwr_domain_coordination()
102 if (IS_PLAT_MCUSYSOFF_AFFLV(state->pwr.afflv)) { in pwr_domain_coordination()
106 ret = fn(state->pwr.afflv, state, &tp); in pwr_domain_coordination()
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| H A D | rules.mk | 14 LOCAL_SRCS-y := ${LOCAL_DIR}/pwr.c
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| /rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv3_2/ |
| H A D | mt_cpu_pm.c | 112 .pwr = { in cpupm_smp_init()
150 unsigned int stateid = state->pwr.state_id; in mcusys_prepare_suspend()
206 if (!state || (state->pwr.afflv > PLAT_MAX_PWR_LVL)) { in cpupm_do_pstate_off()
210 switch (state->pwr.state_id) { in cpupm_do_pstate_off()
224 if (!IS_MT_PLAT_PWR_STATE_MCUSYS(state->pwr.state_id) && in cpupm_do_pstate_off()
225 !IS_PLAT_SYSTEM_SUSPEND(state->pwr.afflv)) { in cpupm_do_pstate_off()
235 if ((mt_pwr_nodes[MT_PWR_NONMCUSYS] == 0) && IS_PLAT_MCUSYSOFF_AFFLV(state->pwr.afflv)) { in cpupm_do_pstate_off()
245 if (state->pwr.afflv >= PLAT_MT_CPU_SUSPEND_CLUSTER) { in cpupm_do_pstate_off()
263 if (state->pwr.afflv > PLAT_MAX_PWR_LVL) { in cpupm_do_pstate_on()
275 if (state->pwr.afflv >= PLAT_MT_CPU_SUSPEND_CLUSTER) { in cpupm_do_pstate_on()
[all …]
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| /rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv5_4/ |
| H A D | mt_cpu_pm.h | 57 _p.pwr.ppu_pwpr = CLUSTER_PPU_PWPR_##_cl; \
58 _p.pwr.ppu_pwsr = CLUSTER_PPU_PWSR_##_cl; \
59 _p.pwr.ppu_dcdr0 = CLUSTER_PPU_DCDR0_##_cl; \
60 _p.pwr.ppu_dcdr1 = CLUSTER_PPU_DCDR1_##_cl; \
76 _p.pwr.ppu_pwpr = CORE_PPU_PWPR_##_cl##_##_c; \
77 _p.pwr.ppu_pwsr = CORE_PPU_PWSR_##_cl##_##_c; \
78 _p.pwr.ppu_dcdr0 = CORE_PPU_DCDR0_##_cl##_##_c; \
79 _p.pwr.ppu_dcdr1 = CORE_PPU_DCDR1_##_cl##_##_c; })
208 struct ppu_pwr_ctrl pwr; member
213 struct ppu_pwr_ctrl pwr; member
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| H A D | mt_cpu_pm.c | 115 IS_PLAT_SUSPEND_ID(__st->pwr.state_id)
134 mt_smp_ppu_pwr_set(&cls_pwr_ctrl.pwr, PPU_PWPR_DYNAMIC_MODE, in cpupm_cluster_resume_common()
305 .pwr = { in cpupm_smp_init()
323 mt_smp_ppu_op_set(&cls_pwr_ctrl.pwr, in cpupm_smp_init()
345 stateid = state->pwr.state_id; in mcusys_prepare_suspend()
416 unsigned int stateid = state->pwr.state_id; in mtk_cpu_pm_mcusys_record()
544 if (!state || (state->pwr.afflv > PLAT_MAX_PWR_LVL)) { in cpupm_do_pstate_off()
546 CPU_PM_ASSERT(state->pwr.afflv <= PLAT_MAX_PWR_LVL); in cpupm_do_pstate_off()
553 switch (state->pwr.state_id) { in cpupm_do_pstate_off()
585 if (state->pwr.afflv > PLAT_MAX_PWR_LVL) in cpupm_do_pstate_on()
[all …]
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| H A D | mt_smp.c | 21 (!!((mmio_read_32(_pwr_ctrl->pwr.ppu_pwsr)) & (PPU_PWSR_STATE_ON)))
60 mt_smp_ppu_pwr_set(&pwr_ctrl->pwr, PPU_PWPR_DYNAMIC_MODE, PPU_PWPR_OFF); in mt_smp_power_core_on()
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| /rk3399_ARM-atf/plat/mediatek/lib/pm/armv8_2/ |
| H A D | pwr_ctrl.c | 161 if (IS_PLAT_SYSTEM_RETENTION(state->pwr.afflv)) { in armv8_2_cpu_pwr_on_common()
239 .pwr = { in armv8_2_power_domain_on_finish()
264 .pwr = { in armv8_2_power_domain_off()
290 pm_state.pwr.state_id = armv8_2_get_pwr_stateid(pm_state.info.cpuid); in armv8_2_power_domain_suspend()
291 pm_state.pwr.afflv = armv8_2_get_pwr_afflv(state); in armv8_2_power_domain_suspend()
292 pm_state.pwr.raw = state; in armv8_2_power_domain_suspend()
328 pm_state.pwr.state_id = armv8_2_get_pwr_stateid(pm_state.info.cpuid); in armv8_2_power_domain_suspend_finish()
329 pm_state.pwr.afflv = armv8_2_get_pwr_afflv(state); in armv8_2_power_domain_suspend_finish()
330 pm_state.pwr.raw = state; in armv8_2_power_domain_suspend_finish()
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| /rk3399_ARM-atf/plat/mediatek/lib/pm/armv9_0/ |
| H A D | pwr_ctrl.c | 222 .pwr = { in power_domain_on_finish()
248 .pwr = { in power_domain_off()
276 pm_state.pwr.state_id = get_pwr_stateid(pm_state.info.cpuid); in power_domain_suspend()
277 pm_state.pwr.afflv = get_pwr_afflv(state); in power_domain_suspend()
278 pm_state.pwr.raw = state; in power_domain_suspend()
310 pm_state.pwr.state_id = get_pwr_stateid(pm_state.info.cpuid); in power_domain_suspend_finish()
311 pm_state.pwr.afflv = get_pwr_afflv(state); in power_domain_suspend_finish()
312 pm_state.pwr.raw = state; in power_domain_suspend_finish()
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| /rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/topology/inc/ |
| H A D | pwr_topology.h | 30 unsigned int pwr_domain_coordination(enum pwr_domain_status pwr,
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/ |
| H A D | mt_spm_common_v1.h | 13 uint32_t pwr; member
19 ({ _info.pwr = _info.pwr_msb = _info.module_busy = 0; })
22 _info.pwr = REG_PWR_STATUS_##_name_##_REQ_MASK; \
27 _info.pwr = SPM_HWCG_##_name_##_PWR_MB; \
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| /rk3399_ARM-atf/include/drivers/st/ |
| H A D | stm32mp_ddr.h | 52 uintptr_t pwr; member
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| /rk3399_ARM-atf/fdts/ |
| H A D | stm32mp151.dtsi | 206 pwr_regulators: pwr@50001000 {
207 compatible = "st,stm32mp1,pwr-reg";
231 compatible = "st,stm32mp151-pwr-mcu", "syscon";
235 pwr_irq: pwr@50001020 {
236 compatible = "st,stm32mp1-pwr";
250 * EXTI 55 to 60. It's mapped on pwr interrupt
253 exti_pwr: exti-pwr {
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| H A D | stm32mp251.dtsi | 323 pwr: pwr@44210000 { label
324 compatible = "st,stm32mp25-pwr";
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| H A D | fvp-base-psci-common.dtsi | 37 max-pwr-lvl = <2>;
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| H A D | stm32mp257d-ultra-fly-sbc.dts | 141 &pwr {
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| H A D | stm32mp257f-dk.dts | 161 &pwr {
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/ |
| H A D | mt_spm_hwreq.c | 56 reg = info->pwr; in spm_hwcg_ctrl_get()
105 if (info.pwr) in spm_hwcg_ctrl()
138 if (!info.pwr) in spm_hwcg_mask_get()
170 if (!info.pwr) in spm_hwcg_get_default()
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/ |
| H A D | mt_spm_hwreq.c | 56 reg = info->pwr; in spm_hwcg_ctrl_get()
105 if (info.pwr) in spm_hwcg_ctrl()
138 if (!info.pwr) in spm_hwcg_mask_get()
170 if (!info.pwr) in spm_hwcg_get_default()
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| /rk3399_ARM-atf/drivers/st/ddr/ |
| H A D | stm32mp1_ram.c | 147 priv->pwr = stm32mp_pwr_base(); in stm32mp1_ddr_probe()
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| H A D | stm32mp2_ddr.c | 383 ddr_retdis = mmio_read_32(priv->pwr + PWR_CR11) & PWR_CR11_DDRRETDIS; in stm32mp2_ddr_init()
395 mmio_setbits_32(priv->pwr + PWR_CR11, PWR_CR11_DDRRETDIS); in stm32mp2_ddr_init()
410 mmio_setbits_32(priv->pwr + PWR_CR11, PWR_CR11_DDRRETDIS); in stm32mp2_ddr_init()
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| H A D | stm32mp2_ram.c | 200 priv->pwr = stm32mp_pwr_base(); in stm32mp2_ddr_probe()
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| /rk3399_ARM-atf/plat/mediatek/lib/pm/ |
| H A D | mtk_pm.h | 98 struct mtk_cpu_pm_state pwr; member
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| /rk3399_ARM-atf/plat/mediatek/include/lib/pm/ |
| H A D | mtk_pm.h | 106 struct mtk_cpu_pm_state pwr; member
|