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Searched refs:pstate (Results 1 – 25 of 40) sorted by relevance

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/rk3399_ARM-atf/plat/imx/imx8m/ddr/
H A Dddr4_dvfs.c77 void dram_cfg_all_mr(struct dram_info *info, uint32_t pstate) in dram_cfg_all_mr() argument
89 ddr4_mr_write(j, info->mr_table[pstate][j], 0, i, dram_type); in dram_cfg_all_mr()
91 ddr4_mr_write(6, info->mr_table[pstate][7], 0, i, dram_type); in dram_cfg_all_mr()
95 void sw_pstate(uint32_t pstate, uint32_t drate) in sw_pstate() argument
105 mmio_write_32(DDRC_MSTR2(0), pstate); in sw_pstate()
126 mmio_write_32(DDRC_DFIMISC(0), 0x00000000 | (pstate << 8)); in sw_pstate()
127 mmio_write_32(DDRC_DFIMISC(0), 0x00000020 | (pstate << 8)); in sw_pstate()
137 mmio_write_32(DDRC_DFIMISC(0), 0x00000000 | (pstate << 8)); in sw_pstate()
161 void ddr4_swffc(struct dram_info *info, unsigned int pstate) in ddr4_swffc() argument
163 uint32_t drate = info->timing_info->fsp_table[pstate]; in ddr4_swffc()
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/rk3399_ARM-atf/plat/mediatek/lib/pm/armv8_2/
H A Dpwr_ctrl.c153 static void armv8_2_cpu_pwr_on_common(const struct mtk_cpupm_pwrstate *state, unsigned int pstate) in armv8_2_cpu_pwr_on_common() argument
169 static void armv8_2_cpu_pwr_dwn_common(const struct mtk_cpupm_pwrstate *state, unsigned int pstate) in armv8_2_cpu_pwr_dwn_common() argument
171 if ((pstate & MT_CPUPM_PWR_DOMAIN_PERCORE_DSU) != 0) { in armv8_2_cpu_pwr_dwn_common()
180 static void armv8_2_cpu_pwr_resume(const struct mtk_cpupm_pwrstate *state, unsigned int pstate) in armv8_2_cpu_pwr_resume() argument
182 armv8_2_cpu_pwr_on_common(state, pstate); in armv8_2_cpu_pwr_resume()
188 static void armv8_2_cpu_pwr_suspend(const struct mtk_cpupm_pwrstate *state, unsigned int pstate) in armv8_2_cpu_pwr_suspend() argument
193 armv8_2_cpu_pwr_dwn_common(state, pstate); in armv8_2_cpu_pwr_suspend()
196 static void armv8_2_cpu_pwr_on(const struct mtk_cpupm_pwrstate *state, unsigned int pstate) in armv8_2_cpu_pwr_on() argument
198 armv8_2_cpu_pwr_on_common(state, pstate); in armv8_2_cpu_pwr_on()
205 static void armv8_2_cpu_pwr_off(const struct mtk_cpupm_pwrstate *state, unsigned int pstate) in armv8_2_cpu_pwr_off() argument
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/rk3399_ARM-atf/plat/mediatek/lib/pm/armv9_0/
H A Dpwr_ctrl.c146 unsigned int pstate) in cpu_pwr_on_common() argument
154 unsigned int pstate) in cpu_pwr_dwn_common() argument
156 if (pstate & MT_CPUPM_PWR_DOMAIN_PERCORE_DSU) in cpu_pwr_dwn_common()
163 unsigned int pstate) in cpu_pwr_resume() argument
165 cpu_pwr_on_common(state, pstate); in cpu_pwr_resume()
171 unsigned int pstate) in cpu_pwr_suspend() argument
175 cpu_pwr_dwn_common(state, pstate); in cpu_pwr_suspend()
179 unsigned int pstate) in cpu_pwr_on() argument
181 cpu_pwr_on_common(state, pstate); in cpu_pwr_on()
187 unsigned int pstate) in cpu_pwr_off() argument
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/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/topology/default/
H A Dpwr.c51 unsigned int pstate = 0; in pwr_domain_coordination() local
63 return pstate; in pwr_domain_coordination()
79 pstate |= MT_CPUPM_PWR_DOMAIN_CLUSTER; in pwr_domain_coordination()
82 pstate |= MT_CPUPM_PWR_DOMAIN_PERCORE_DSU; in pwr_domain_coordination()
94 pstate |= MT_CPUPM_PWR_DOMAIN_MCUSYS; in pwr_domain_coordination()
104 pstate |= MT_CPUPM_PWR_DOMAIN_MCUSYS; in pwr_domain_coordination()
119 return pstate; in pwr_domain_coordination()
/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv3_2/
H A Dmt_cpu_pm.c204 unsigned int pstate = MT_CPUPM_PWR_DOMAIN_CORE; in cpupm_do_pstate_off() local
241 pstate |= (MT_CPUPM_PWR_DOMAIN_MCUSYS | MT_CPUPM_PWR_DOMAIN_CLUSTER); in cpupm_do_pstate_off()
246 pstate |= MT_CPUPM_PWR_DOMAIN_CLUSTER; in cpupm_do_pstate_off()
250 pstate |= MT_CPUPM_PWR_DOMAIN_PERCORE_DSU; in cpupm_do_pstate_off()
253 return pstate; in cpupm_do_pstate_off()
259 unsigned int pstate = MT_CPUPM_PWR_DOMAIN_CORE; in cpupm_do_pstate_on() local
271 pstate |= (MT_CPUPM_PWR_DOMAIN_MCUSYS | MT_CPUPM_PWR_DOMAIN_CLUSTER); in cpupm_do_pstate_on()
276 pstate |= MT_CPUPM_PWR_DOMAIN_CLUSTER; in cpupm_do_pstate_on()
317 pstate |= MT_CPUPM_PWR_DOMAIN_PERCORE_DSU; in cpupm_do_pstate_on()
319 return pstate; in cpupm_do_pstate_on()
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/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/topology/group_4_3_1/
H A Dpwr.c65 unsigned int pstate = MT_CPUPM_PWR_DOMAIN_CORE; in pwr_domain_coordination() local
92 pstate |= MT_CPUPM_PWR_DOMAIN_CLUSTER; in pwr_domain_coordination()
97 return pstate; in pwr_domain_coordination()
100 pstate |= MT_CPUPM_PWR_DOMAIN_PERCORE_DSU; in pwr_domain_coordination()
109 pstate |= MT_CPUPM_PWR_DOMAIN_MCUSYS; in pwr_domain_coordination()
112 return pstate; in pwr_domain_coordination()
/rk3399_ARM-atf/include/drivers/arm/
H A Dccn.h41 #define CCN_GET_RETENTION_STATE(pstate) ((pstate >> 4) & 0x3) argument
47 #define CCN_GET_RUN_STATE(pstate) (pstate & 0xf) argument
/rk3399_ARM-atf/drivers/imx/usdhc/
H A Dimx_usdhc.c116 uint32_t pstate; in imx_usdhc_set_clk() local
132 ret = mmio_read_32_poll_timeout(reg_base + PSTATE, pstate, in imx_usdhc_set_clk()
133 (pstate & PSTATE_SDSTB) != 0U, in imx_usdhc_set_clk()
265 uint32_t xfertype, pstate, intstat, sysctrl; in imx_usdhc_send_cmd() local
283 err = mmio_read_32_poll_timeout(reg_base + PSTATE, pstate, in imx_usdhc_send_cmd()
284 (pstate & (PSTATE_CDIHB | PSTATE_CIHB)) == 0U, in imx_usdhc_send_cmd()
291 err = mmio_read_32_poll_timeout(reg_base + PSTATE, pstate, in imx_usdhc_send_cmd()
292 (pstate & PSTATE_DLA) == 0U, in imx_usdhc_send_cmd()
/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv5_4/
H A Dmt_cpu_pm.c537 unsigned int pstate = MT_CPUPM_PWR_DOMAIN_CORE; in cpupm_do_pstate_off() local
540 pstate &= ~(MT_CPUPM_PWR_DOMAIN_CLUSTER | in cpupm_do_pstate_off()
563 pstate |= pwr_domain_coordination(PWR_DOMAIN_OFF, in cpupm_do_pstate_off()
570 return pstate; in cpupm_do_pstate_off()
576 unsigned int pstate = MT_CPUPM_PWR_DOMAIN_CORE; in cpupm_do_pstate_on() local
579 pstate &= ~(MT_CPUPM_PWR_DOMAIN_CLUSTER | in cpupm_do_pstate_on()
601 pstate |= pwr_domain_coordination(PWR_DOMAIN_ON, in cpupm_do_pstate_on()
606 return pstate; in cpupm_do_pstate_on()
702 unsigned int pstate = 0; in cpupm_get_pstate() local
708 pstate = MT_CPUPM_PWR_DOMAIN_CORE; in cpupm_get_pstate()
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/rk3399_ARM-atf/plat/arm/common/
H A Darm_pm.c27 unsigned int pstate = psci_get_pstate_type(power_state); in arm_validate_power_state() local
37 if (pstate == PSTATE_TYPE_STANDBY) { in arm_validate_power_state()
/rk3399_ARM-atf/drivers/arm/ccn/
H A Dccn_private.h161 #define PSTATE_TO_RUN_MODE(pstate) (((pstate) & HNF_PSTATE_MASK) >> 2) argument
/rk3399_ARM-atf/plat/hisilicon/poplar/
H A Dplat_pm.c118 int pstate = psci_get_pstate_type(power_state); in poplar_validate_power_state() local
123 if (pstate == PSTATE_TYPE_STANDBY) in poplar_validate_power_state()
/rk3399_ARM-atf/plat/renesas/rcar_gen5/
H A Dplat_pm.c166 uint32_t pstate = psci_get_pstate_type(power_state); in rcar_validate_power_state() local
169 if (pstate == PSTATE_TYPE_STANDBY) { in rcar_validate_power_state()
/rk3399_ARM-atf/plat/imx/imx8m/include/
H A Ddram.h91 void ddr4_swffc(struct dram_info *dram_info, unsigned int pstate);
/rk3399_ARM-atf/plat/hisilicon/hikey/
H A Dhikey_pm.c217 int pstate = psci_get_pstate_type(power_state); in hikey_validate_power_state() local
227 if (pstate == PSTATE_TYPE_STANDBY) { in hikey_validate_power_state()
/rk3399_ARM-atf/plat/xilinx/zynqmp/
H A Dplat_psci.c218 uint32_t pstate = psci_get_pstate_type(power_state); in zynqmp_validate_power_state() local
224 if (pstate == PSTATE_TYPE_STANDBY) { in zynqmp_validate_power_state()
/rk3399_ARM-atf/plat/renesas/rcar_gen4/
H A Dplat_pm.c162 uint32_t pstate = psci_get_pstate_type(power_state); in rcar_validate_power_state() local
165 if (pstate == PSTATE_TYPE_STANDBY) { in rcar_validate_power_state()
/rk3399_ARM-atf/plat/brcm/board/stingray/src/
H A Dbrcm_pm_ops.c347 int pstate = psci_get_pstate_type(power_state); in brcm_validate_power_state() local
357 if (pstate == PSTATE_TYPE_STANDBY) { in brcm_validate_power_state()
/rk3399_ARM-atf/plat/xilinx/versal/
H A Dplat_psci.c281 uint32_t pstate = psci_get_pstate_type(power_state); in versal_validate_power_state() local
286 if (pstate == PSTATE_TYPE_STANDBY) { in versal_validate_power_state()
/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/src/
H A Dddrphy_phyinit_softsetmb.c41 mb_ddr_1d->pstate = (uint8_t)value; in ddrphy_phyinit_softsetmb()
/rk3399_ARM-atf/plat/hisilicon/hikey960/
H A Dhikey960_pm.c141 unsigned int pstate = psci_get_pstate_type(power_state); in hikey960_validate_power_state() local
151 if (pstate == PSTATE_TYPE_STANDBY) { in hikey960_validate_power_state()
/rk3399_ARM-atf/plat/ti/k3/common/
H A Dk3_psci.c232 unsigned int pstate = psci_get_pstate_type(power_state); in k3_validate_power_state() local
237 if (pstate == PSTATE_TYPE_STANDBY) { in k3_validate_power_state()
/rk3399_ARM-atf/plat/xilinx/versal_net/
H A Dplat_psci_pm.c314 uint32_t pstate = psci_get_pstate_type(power_state); in versal_net_validate_power_state() local
319 if (pstate == PSTATE_TYPE_STANDBY) { in versal_net_validate_power_state()
/rk3399_ARM-atf/include/lib/psci/
H A Dpsci.h120 #define psci_get_pstate_pwrlvl(pstate) (((pstate) >> PSTATE_PWR_LVL_SHIFT) & \ argument
/rk3399_ARM-atf/plat/rockchip/common/
H A Dplat_pm.c133 int pstate = psci_get_pstate_type(power_state); in rockchip_validate_power_state() local
143 if (pstate == PSTATE_TYPE_STANDBY) { in rockchip_validate_power_state()

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