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/rk3399_ARM-atf/docs/design_documents/
H A Dpsci_osi_mode.rst17 A power domain topology is a logical hierarchy of power domains in a system that
18 arises from the physical dependencies between power domains.
20 Local power states describe power states for an individual node, and composite
21 power states describe the combined power states for an individual node and its
24 Entry into low-power states for a topology node above the core level requires
25 coordinating its children nodes. For example, in a system with a power domain
26 that encompasses a shared cache, and a separate power domain for each core that
27 uses the shared cache, the core power domains must be powered down before the
28 shared cache power domain can be powered down.
30 PSCI supports two modes of power state coordination: platform-coordinated and
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/rk3399_ARM-atf/docs/design/
H A Dpsci-pd-tree.rst9 populate a tree that describes the hierarchy of power domains in the
13 It would be much simpler for the platform to describe its power domain tree
16 #. The generic PSCI code generates MPIDRs in order to populate the power domain
20 levels in the power domain tree to four.
23 mechanism used to populate the power domain topology tree.
25 #. The current arrangement of the power domain tree requires a binary search
26 over the sibling nodes at a particular level to find a specified power
27 domain node. During a power management operation, the tree is traversed from
28 a 'start' to an 'end' power level. The binary search is required to find the
36 #. The attributes of a core power domain differ from the attributes of power
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/rk3399_ARM-atf/docs/perf/
H A Dpsci-performance-n1sdp.rst21 ``CPU_SUSPEND`` to deepest power level
23 .. table:: ``CPU_SUSPEND`` latencies (ns) to deepest power level in parallel (v2.14)
37 .. table:: ``CPU_SUSPEND`` latencies (ns) to deepest power level in parallel (v2.13)
51 .. table:: ``CPU_SUSPEND`` latencies (ns) to deepest power level in serial (v2.14)
65 .. table:: ``CPU_SUSPEND`` latencies (ns) to deepest power level in serial (v2.13)
79 ``CPU_SUSPEND`` to power level 0
82 .. table:: ``CPU_SUSPEND`` latencies (ns) to power level 0 in parallel (v2.14)
96 .. table:: ``CPU_SUSPEND`` latencies (ns) to power level 0 in parallel (v2.13)
110 .. table:: ``CPU_SUSPEND`` latencies (ns) to power level 0 in serial (v2.14)
124 .. table:: ``CPU_SUSPEND`` latencies (ns) to power level 0 in serial (v2.13)
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H A Dpsci-performance-juno.rst25 Juno supports CPU, cluster and system power down states, corresponding to power
46 ``CPU_SUSPEND`` to deepest power level
49 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
68 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
87 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
106 .. table:: ``CPU_SUSPEND`` latencies (µs) to deepest power level in
125 ``CPU_SUSPEND`` to power level 0
128 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
147 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in
166 .. table:: ``CPU_SUSPEND`` latencies (µs) to power level 0 in serial (v2.14)
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H A Dpsci-performance-instr.rst43 power states used by the platform. The service tracks residency time and
44 entry count. Residency time is the total time spent in a particular power
46 the power state. PSCI Statistics implements the optional functions
73 The implementation provides residency statistics only for low power states,
97 * Entry to low power state
98 * Exit from low power state
111 captured after normal return from the PSCI SMC handler, or, if a low power state
H A Dpsci-performance-methodology.rst45 enters the low power state (WFI). Referring to the TF runtime instrumentation points, this
49 Time taken from the point the hardware exits the low power state to exiting
/rk3399_ARM-atf/docs/components/
H A Dmpmm.rst4 |MPMM| is an optional microarchitectural power management mechanism supported by
7 assist in |SoC| processor power domain dynamic power budgeting and limit the
16 external power controller can use these metrics to budget SoC power by
/rk3399_ARM-atf/plat/intel/soc/n5x/soc/
H A Dn5x_clock_manager.c24 uint32_t power = 1; in clk_get_pll_output_hz() local
54 power *= 2; in clk_get_pll_output_hz()
58 return ((clock * 2 * (divf + 1)) / ((divr + 1) * power)); in clk_get_pll_output_hz()
/rk3399_ARM-atf/docs/
H A Dporting-guide.rst152 Defines the total number of nodes in the power domain topology
153 tree at all the power domain levels used by the platform.
155 data structures to represent power domain topology.
159 Defines the maximum power domain level that the power management operations
160 should apply to. More often, but not always, the power domain level
162 to know the highest power domain level that it should consider for power
165 number of CPUs and it reports the maximum power domain level as 1.
169 Defines the local power state corresponding to the deepest power down
170 possible at every power domain level in the platform. The local power
173 value to initialize the local power states of the power domain nodes and
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/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_vcorefs.c455 int power = 0; in spm_vcorefs_vcore_setting() local
477 power = (int)devinfo_table[idx]; in spm_vcorefs_vcore_setting()
480 if (power > 0 && power <= 40) { in spm_vcorefs_vcore_setting()
/rk3399_ARM-atf/docs/plat/
H A Dallwinner.rst50 to be loaded into the ARISC SCP (A64, H5), or the power sequence control
59 This allows more advanced power saving techniques, like suspend to RAM.
66 power management controller, BL31 tries to set up all needed power rails,
68 software like U-Boot to ignore power control via the PMIC.
H A Dimx8ulp.rst4 i.MX 8ULP is part of the ULP family with emphasis on extreme low-power techniques
12 Tensilica Fusion DSP for low-power audio and a HiFi4 DSP for advanced audio and machine
16 separate power, clocking and peripheral islands, but the bus fabric of each domain
H A Dxilinx-versal-net.rst49 * `CPU_PWRDWN_SGI`: Select the SGI for triggering CPU power down request to
50 secondary cores on receiving power down callback from
H A Dxilinx-zynqmp.rst114 The following power domain tree represents the power domain model used by TF-A
130 The 4 leaf power domains represent the individual A53 cores, while resources
131 common to the cluster are grouped in the power domain on the top.
H A Dnvidia-tegra.rst53 Denver also features new low latency power-state transitions, in addition
54 to extensive power-gating and dynamic voltage and clock scaling based on
141 The PSCI implementation expects each platform to expose the 'power state'
151 be enabled by Tegrs SoCs during 'Cluster power up' or 'System Suspend' exit.
H A Dhikey.rst122 - Make sure Pin3-Pin4 on J15 are connected for recovery mode. Then power on HiKey.
151 - Make sure Pin3-Pin4 on J15 are open for normal boot mode. Then power on HiKey.
/rk3399_ARM-atf/plat/arm/board/fvp/fdts/
H A Dfvp_tsp_sp_manifest.dts26 power-management-messages = <0x7>;
/rk3399_ARM-atf/plat/allwinner/common/
H A Darisc_off.S32 # - Finally turn off the core's power switch by writing 0xff to the
64 1: l.lwz r5, 0x1c30(r13) # CPU power-on reset
74 l.sw 0x1540(r6), r5 # core power switch registers
/rk3399_ARM-atf/plat/imx/imx8ulp/scmi/
H A Dscmi_sensor.c68 desc->power = 0; in imx_scmi_sensor_description_get()
/rk3399_ARM-atf/drivers/st/bsec/
H A Dbsec2.c36 static uint32_t bsec_power_safmem(bool power);
741 static uint32_t bsec_power_safmem(bool power) in bsec_power_safmem() argument
750 if (power) { in bsec_power_safmem()
758 if (power) { in bsec_power_safmem()
/rk3399_ARM-atf/drivers/scmi-msg/
H A Dsensor.h49 uint32_t power; member
/rk3399_ARM-atf/docs/plat/arm/
H A Darm-build-options.rst56 for the construction of composite state-ID in the power-state parameter.
61 field of power-state parameter.
133 instead of SCPI/BOM driver for communicating with the SCP during power
139 require all the CPUs to execute the CPU specific power down sequence to
140 complete a warm reboot sequence in which only the CPUs are power cycled.
/rk3399_ARM-atf/docs/resources/diagrams/plantuml/
H A Drse_attestation_flow.puml38 Rnote over RMM: Platform token is\n\ cached. It is not\n\ changing within\n\ a power cycle.
/rk3399_ARM-atf/docs/about/
H A Dfeatures.rst17 - Library support for CPU specific reset and power down sequences. This
31 - |PSCI| library support for CPU, cluster and system power management
37 - A generic |SCMI| driver to interface with conforming power controllers, for
/rk3399_ARM-atf/docs/plat/nxp/
H A Dnxp-layerscape.rst13 Layerscape family, combines FinFET process technology's low power and
61 power supply and single clock design. The new 0.9V versions of the LS1043A
62 and LS1023A deliver addition power savings for applications such as Wireless
100 The LS1046A is a cost-effective, power-efficient, and highly integrated
102 line of QorIQ communications processors. Featuring power-efficient 64-bit

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