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123

/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/usercustom/
H A Dddrphy_phyinit_usercustom_custompretrain.c49 uint32_t j; in ddrphy_phyinit_usercustom_custompretrain() local
62 for (j = 0U; j < NB_AC_SWIZZLE; j++, i++) { in ddrphy_phyinit_usercustom_custompretrain()
63 mmio_write_32(base + (j * sizeof(uint32_t)), config->uis.swizzle[i]); in ddrphy_phyinit_usercustom_custompretrain()
70 for (j = 0U; j < NB_DQLNSEL_SWIZZLE_PER_BYTE; j++, i++) { in ddrphy_phyinit_usercustom_custompretrain()
71 mmio_write_16(base + (j * sizeof(uint32_t)), in ddrphy_phyinit_usercustom_custompretrain()
78 for (j = 0U; j < NB_MAPCAATODFI_SWIZZLE; j++, i++) { in ddrphy_phyinit_usercustom_custompretrain()
79 mmio_write_16(base + (j * sizeof(uint32_t)), in ddrphy_phyinit_usercustom_custompretrain()
85 for (j = 0U; j < NB_MAPCABTODFI_SWIZZLE; j++, i++) { in ddrphy_phyinit_usercustom_custompretrain()
86 mmio_write_16(base + (j * sizeof(uint32_t)), in ddrphy_phyinit_usercustom_custompretrain()
/rk3399_ARM-atf/plat/imx/imx8ulp/
H A Dapd_context.c148 unsigned int i, j; in apd_io_pad_off() local
152 for (j = 0; j < iomuxc_sections[i].reg_num; j++) { in apd_io_pad_off()
153 mmio_write_32(iomuxc_sections[i].offset + j * 4, 0); in apd_io_pad_off()
163 unsigned int i, j; in iomuxc_save() local
167 for (j = 0U; j < iomuxc_sections[i].reg_num; j++) { in iomuxc_save()
168 iomuxc_ctx[index++] = mmio_read_32(iomuxc_sections[i].offset + j * 4); in iomuxc_save()
177 unsigned int i, j; in iomuxc_restore() local
181 for (j = 0U; j < iomuxc_sections[i].reg_num; j++) { in iomuxc_restore()
182 mmio_write_32(iomuxc_sections[i].offset + j * 4, iomuxc_ctx[index++]); in iomuxc_restore()
189 unsigned int i, j; in gpio_save() local
[all …]
/rk3399_ARM-atf/lib/psci/
H A Dpsci_setup.c100 int j; in psci_update_pwrlvl_limits() local
108 for (j = (int)PLAT_MAX_PWR_LVL - 1; j >= 0; j--) { in psci_update_pwrlvl_limits()
109 if (temp_index[j] != nodes_idx[j]) { in psci_update_pwrlvl_limits()
110 nodes_idx[j] = temp_index[j]; in psci_update_pwrlvl_limits()
111 psci_non_cpu_pd_nodes[nodes_idx[j]].cpu_start_idx in psci_update_pwrlvl_limits()
114 psci_non_cpu_pd_nodes[nodes_idx[j]].ncpus++; in psci_update_pwrlvl_limits()
135 unsigned int i, j = 0U, num_nodes_at_lvl = 1U, num_nodes_at_next_lvl; in populate_power_domain_tree() local
164 for (j = node_index; in populate_power_domain_tree()
165 j < (node_index + num_children); j++) { in populate_power_domain_tree()
166 psci_init_pwr_domain_node((uint16_t)j, in populate_power_domain_tree()
[all …]
/rk3399_ARM-atf/plat/imx/imx8ulp/xrdc/
H A Dxrdc_core.c229 unsigned int i, j; in xrdc_apply_config() local
247 for (j = 0U; j < DID_MAX; j++) { in xrdc_apply_config()
248 val |= imx8ulp_mrc[i].dsel[j] << (3 * j); in xrdc_apply_config()
260 for (j = 0U; j < DID_MAX; j++) { in xrdc_apply_config()
261 val |= imx8ulp_pdac[i].dsel[j] << (3 * j); in xrdc_apply_config()
266 for (j = 0U; j < imx8ulp_pac_slots[imx8ulp_pdac[i].pac_msc_id]; j++) { in xrdc_apply_config()
267 xrdc_config_pac(imx8ulp_pdac[i].pac_msc_id, j, val); in xrdc_apply_config()
282 for (j = 0U; j < DID_MAX; j++) { in xrdc_apply_config()
283 val |= imx8ulp_msc[i].dsel[j] << (3 * j); in xrdc_apply_config()
288 for (j = 0U; j < imx8ulp_msc_slots[imx8ulp_msc[i].pac_msc_id]; j++) { in xrdc_apply_config()
[all …]
/rk3399_ARM-atf/plat/intel/soc/common/soc/
H A Dsocfpga_handoff.c19 int j; in socfpga_get_handoff() local
28 for (j = 0; j < sizeof(handoff) / 4; j++) { in socfpga_get_handoff()
29 memcpy_s((void *) (reverse_hoff_ptr_dst + j), 1, in socfpga_get_handoff()
30 (void *) (handoff_ptr + j), 1); in socfpga_get_handoff()
/rk3399_ARM-atf/drivers/nxp/clk/s32cc/
H A Ds32cc_clk_utils.c51 size_t i, j; in s32cc_get_id_from_table() local
54 for (j = 0; j < clk_arr[i]->n_clks; j++) { in s32cc_get_id_from_table()
55 if (clk_arr[i]->clks[j] != clk) { in s32cc_get_id_from_table()
59 *clk_index = S32CC_CLK(clk_arr[i]->type_mask, j); in s32cc_get_id_from_table()
/rk3399_ARM-atf/drivers/qti/accesscontrol/
H A Dxpu.c40 for (int j = 0; j < xpu->part_range_arr_size; j++) { in qti_msm_xpu_bypass() local
41 xpu->partition_range[j].start_addr = 0xffffffff; in qti_msm_xpu_bypass()
42 xpu->partition_range[j].end_addr = 0xffffffff; in qti_msm_xpu_bypass()
/rk3399_ARM-atf/plat/arm/board/neoverse_rd/platform/rdn2/
H A Drdn2_security.c60 unsigned int j; in plat_arm_security_setup() local
65 for (j = 0; j < TZC400_COUNT; j++) { in plat_arm_security_setup()
67 + TZC400_BASE(j), tzc_regions_mc[i-1]); in plat_arm_security_setup()
/rk3399_ARM-atf/plat/rockchip/common/
H A Dplat_pm_helpers.c92 int i, j; in rockchip_reg_rgn_save() local
98 for (j = 0, addr = r->start; addr <= r->end; addr += r->stride, j++) in rockchip_reg_rgn_save()
99 r->buf[j] = mmio_read_32(addr); in rockchip_reg_rgn_save()
112 int i, j; in rockchip_reg_rgn_restore() local
118 for (j = 0, addr = r->start; addr <= r->end; addr += r->stride, j++) in rockchip_reg_rgn_restore()
119 mmio_write_32(addr, r->buf[j] | r->wmsk); in rockchip_reg_rgn_restore()
134 int i, j; in rockchip_reg_rgn_restore_reverse() local
140 j = RGN_LEN(r) - 1; in rockchip_reg_rgn_restore_reverse()
141 for (addr = r->end; addr >= r->start; addr -= r->stride, j--) in rockchip_reg_rgn_restore_reverse()
142 mmio_write_32(addr, r->buf[j] | r->wmsk); in rockchip_reg_rgn_restore_reverse()
/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_iossm_mailbox.c195 int i, j, k; in io96b_mb_init() local
203 j = 0; in io96b_mb_init()
222 inst->mb_ctrl.ip_type[j] = ip_type_ret; in io96b_mb_init()
223 inst->mb_ctrl.ip_instance_id[j] = instance_id_ret; in io96b_mb_init()
225 j++; in io96b_mb_init()
488 int i, j; in get_mem_width_info() local
503 for (j = 0; j < instance->mb_ctrl.num_mem_interface; j++) { in get_mem_width_info()
505 mem_total_capacity_intf_offset[j]); in get_mem_width_info()
507 instance->mb_ctrl.memory_size[j] = in get_mem_width_info()
510 if (instance->mb_ctrl.memory_size[j] != 0) in get_mem_width_info()
[all …]
/rk3399_ARM-atf/plat/rockchip/px30/drivers/soc/
H A Dsoc.c48 uint32_t i, j; in clk_gate_con_save() local
53 j = i; in clk_gate_con_save()
54 for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++, j++) in clk_gate_con_save()
55 clkgt_save[j] = in clk_gate_con_save()
61 uint32_t i, j; in clk_gate_con_restore() local
67 j = i; in clk_gate_con_restore()
68 for (i = 0; i < CRU_PMU_CLKGATE_CON_CNT; i++, j++) in clk_gate_con_restore()
70 WITH_16BITS_WMSK(clkgt_save[j])); in clk_gate_con_restore()
/rk3399_ARM-atf/plat/mediatek/mt8173/drivers/crypt/
H A Dcrypt.c59 uint32_t j = 0; in crypt_set_hdcp_key_ex() local
88 for (j = 0; j < 4; j++) { in crypt_set_hdcp_key_ex()
90 crypt_write32(REG_P69, 0x34 + 4 * i + j); in crypt_set_hdcp_key_ex()
91 crypt_write32(REG_P70, record[j]); in crypt_set_hdcp_key_ex()
/rk3399_ARM-atf/tools/encrypt_fw/src/
H A Dencrypt.c31 int bytes, enc_len = 0, i, j, ret = 0; in gcm_encrypt() local
41 for (i = 0, j = 0; i < KEY_SIZE; i++, j += 2) { in gcm_encrypt()
42 if (sscanf(&key_string[j], "%02hhx", &key[i]) != 1) { in gcm_encrypt()
53 for (i = 0, j = 0; i < IV_SIZE; i++, j += 2) { in gcm_encrypt()
54 if (sscanf(&nonce_string[j], "%02hhx", &iv[i]) != 1) { in gcm_encrypt()
/rk3399_ARM-atf/plat/mediatek/drivers/thermal/src/
H A Dthermal_lvts.c237 unsigned int i, j, num; in enable_all_sensing_points() local
255 for (j = 0; j < tc[i].num_sensor; j++) { in enable_all_sensing_points()
256 if (tc[i].sensor_on_off[j] != SEN_ON) in enable_all_sensing_points()
259 flag = flag | (0x1 << j); in enable_all_sensing_points()
448 unsigned int i, j, s_index; in read_calibration_data() local
458 for (j = 0; j < tc[i].num_sensor; j++) { in read_calibration_data()
459 if (tc[i].sensor_on_off[j] != SEN_ON) in read_calibration_data()
462 s_index = tc[i].sensor_map[j]; in read_calibration_data()
465 mmio_read_32(LVTSEDATA00_0 + base + 0x4 * j); in read_calibration_data()
560 unsigned int i, j, s_index; in set_calibration_data_v1() local
[all …]
/rk3399_ARM-atf/lib/zlib/
H A Dzutil.c153 uInt j; in zmemcmp() local
155 for (j = 0; j < len; j++) { in zmemcmp()
156 if (s1[j] != s2[j]) return 2*(s1[j] > s2[j])-1; in zmemcmp()
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t194/
H A Dplat_ras.c106 for (uint32_t j = 0; j < num_idx; j++) { in tegra194_ras_enable() local
121 assert(aux_data[j].err_ctrl != NULL); in tegra194_ras_enable()
128 ser_sys_select_record(idx_start + j); in tegra194_ras_enable()
131 uncorr_errs = aux_data[j].err_ctrl(); in tegra194_ras_enable()
151 idx_start + j, err_fr, err_ctrl); in tegra194_ras_enable()
210 uint32_t j; in tegra194_ras_corrected_err_clear() local
212 j = (i == prev.rec.last_node && prev.value != 0UL) ? in tegra194_ras_corrected_err_clear()
215 for (; j < num_idx; j++) { in tegra194_ras_corrected_err_clear()
218 uint32_t err_idx = idx_start + j; in tegra194_ras_corrected_err_clear()
235 prev.rec.last_idx = j; in tegra194_ras_corrected_err_clear()
/rk3399_ARM-atf/drivers/nxp/flexspi/nor/
H A Dfspi.c285 uint32_t i = 0U, j = 0U, x_rem = 0U; in xspi_ip_read() local
352 for (j = 0U; j < x_size_wm; j += 4U) { in xspi_ip_read()
354 data = fspi_readl(FSPI_RFDR + j); in xspi_ip_read()
375 j = 0U; in xspi_ip_read()
378 data = fspi_readl(FSPI_RFDR + j); in xspi_ip_read()
411 uint32_t i = 0U, j = 0U; in xspi_ip_write() local
446 for (j = 0U; j < x_size_wm; j += 4U) { in xspi_ip_write()
449 fspi_writel((FSPI_TFDR + j), ui_data); in xspi_ip_write()
466 j = 0U; in xspi_ip_write()
472 fspi_writel((FSPI_TFDR + j), ui_data); in xspi_ip_write()
[all …]
/rk3399_ARM-atf/plat/mediatek/drivers/thermal/mt8189/
H A Dsoc_temp_lvts.c309 unsigned int i, j, s_index; in mt8189_device_read_count_rc_n() local
333 for (j = 0; j < tc[i].num_sensor; j++) { in mt8189_device_read_count_rc_n()
334 if (j >= ALL_SENSING_POINTS) in mt8189_device_read_count_rc_n()
337 if (tc[i].sensor_on_off[j] != SEN_ON) in mt8189_device_read_count_rc_n()
340 refine_data_idx[j] = 0xff; in mt8189_device_read_count_rc_n()
341 s_index = tc[i].sensor_map[j]; in mt8189_device_read_count_rc_n()
343 lvts_write_device(lvts_data, SELECT_SENSOR_RCK_V1(j), in mt8189_device_read_count_rc_n()
367 udelay(50 * (j == 0)); in mt8189_device_read_count_rc_n()
376 refine_data_idx[j] = s_index; in mt8189_device_read_count_rc_n()
386 refine_data_idx[j] = s_index; in mt8189_device_read_count_rc_n()
[all …]
/rk3399_ARM-atf/plat/qemu/common/
H A Dqemu_spm.c64 unsigned int i, j; in qemu_initialize_mp_info() local
68 for (j = 0; j < PLATFORM_MAX_CPUS_PER_CLUSTER; j++) { in qemu_initialize_mp_info()
69 tmp->mpidr = (0x80000000 | (i << MPIDR_AFF1_SHIFT)) + j; in qemu_initialize_mp_info()
/rk3399_ARM-atf/drivers/nxp/ddr/nxp-ddr/
H A Dregs.c938 int j; in cal_ddr_addr_dec() local
1031 for (j = 0; j < 18; j++) { in cal_ddr_addr_dec()
1032 if (map_row[j] != i) { in cal_ddr_addr_dec()
1042 for (j = 0; j < 11; j++) { in cal_ddr_addr_dec()
1043 if (map_col[j] != i) { in cal_ddr_addr_dec()
1053 for (j = 0; j < 2; j++) { in cal_ddr_addr_dec()
1054 if (map_ba[j] != i) { in cal_ddr_addr_dec()
1064 for (j = 0; j < 2; j++) { in cal_ddr_addr_dec()
1065 if (map_bg[j] != i) { in cal_ddr_addr_dec()
1075 for (j = 0; j < 2; j++) { in cal_ddr_addr_dec()
[all …]
H A Dddr.c514 int j, valid_mask = 0; in parse_spd() local
535 for (j = 0; j < num_dimm; j++, addr_idx++) { in parse_spd()
536 debug("DIMM %d\n", j); in parse_spd()
539 if (j == 0) { in parse_spd()
577 conf->dimm_in_use[j] = 1; in parse_spd()
621 for (j = 0; j < DDRC_NUM_DIMM; j++) { in parse_spd()
622 if (conf->dimm_in_use[j] == 0) { in parse_spd()
630 conf->cs_on_dimm[j] = 0x3 << (j * CONFIG_CS_PER_SLOT); in parse_spd()
631 conf->cs_in_use |= conf->cs_on_dimm[j]; in parse_spd()
634 conf->cs_on_dimm[j] = 0x1 << (j * CONFIG_CS_PER_SLOT); in parse_spd()
[all …]
/rk3399_ARM-atf/drivers/arm/gic/v3/
H A Dgic600_multichip.c335 unsigned int i, j; in gic600_multichip_lca_init() local
339 for (j = 0; j < multichip_data->chip_count; j++) { in gic600_multichip_lca_init()
340 INFO("RT(LCA): CHIP%u -> CHIP%u 0x%lx\n", i, j, in gic600_multichip_lca_init()
341 multichip_data->chip_addrs[i][j]); in gic600_multichip_lca_init()
342 set_gicd_chipr_n(multichip_data->base_addrs[i], j, in gic600_multichip_lca_init()
343 multichip_data->chip_addrs[i][j], in gic600_multichip_lca_init()
344 multichip_data->spi_ids[j].spi_id_min, in gic600_multichip_lca_init()
345 multichip_data->spi_ids[j].spi_id_max); in gic600_multichip_lca_init()
/rk3399_ARM-atf/plat/imx/imx8m/ddr/
H A Dddr4_dvfs.c88 for (int j = 0; j < 6; j++) { in dram_cfg_all_mr() local
89 ddr4_mr_write(j, info->mr_table[pstate][j], 0, i, dram_type); in dram_cfg_all_mr()
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/pmu/
H A Dpmu.c352 int i, j = 0; in clk_gate_con_save() local
354 for (i = 0; i < CRU_CLKGATE_CON_CNT; i++, j++) in clk_gate_con_save()
355 clk_save[j] = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(i)); in clk_gate_con_save()
357 for (i = 0; i < PHP_CRU_CLKGATE_CON_CNT; i++, j++) in clk_gate_con_save()
358 clk_save[j] = mmio_read_32(PHP_CRU_BASE + PHP_CRU_CLKGATE_CON(i)); in clk_gate_con_save()
360 for (i = 0; i < SECURE_CRU_CLKGATE_CON_CNT; i++, j++) in clk_gate_con_save()
361 clk_save[j] = mmio_read_32(SECURE_CRU_BASE + SECURE_CRU_CLKGATE_CON(i)); in clk_gate_con_save()
363 for (i = 0; i < SECURE_SCRU_CLKGATE_CON_CNT; i++, j++) in clk_gate_con_save()
364 clk_save[j] = mmio_read_32(SECURE_CRU_BASE + SECURE_SCRU_CLKGATE_CON(i)); in clk_gate_con_save()
366 for (i = 0; i < PMU1CRU_CLKGATE_CON_CNT; i++, j++) in clk_gate_con_save()
[all …]
/rk3399_ARM-atf/services/std_svc/sdei/
H A Dsdei_event.c131 unsigned int i, j; in find_event_map() local
139 iterate_mapping(mapping, j, map) { in find_event_map()
156 unsigned int j; in sdei_get_registered_event_count() local
161 iterate_mapping(mapping, j, map) { in sdei_get_registered_event_count()

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