| #
6f802c44 |
| 02-Nov-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "mp/exceptions" into integration
* changes: docs(ras): update RAS documentation docs(el3-runtime): update BL31 exception vector handling fix(el3-runtime): restrict low
Merge changes from topic "mp/exceptions" into integration
* changes: docs(ras): update RAS documentation docs(el3-runtime): update BL31 exception vector handling fix(el3-runtime): restrict lower el EA handlers in FFH mode fix(ras): remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT fix(ras): restrict ENABLE_FEAT_RAS to have only two states feat(ras): use FEAT_IESB for error synchronization feat(el3-runtime): modify vector entry paths
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| #
f87e54f7 |
| 10-Oct-2023 |
Manish Pandey <manish.pandey2@arm.com> |
fix(ras): remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT
This patch removes RAS_FFH_SUPPORT macro which is the combination of ENABLE_FEAT_RAS and HANDLE_EA_EL3_FIRST_NS. Instead introduce an inter
fix(ras): remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT
This patch removes RAS_FFH_SUPPORT macro which is the combination of ENABLE_FEAT_RAS and HANDLE_EA_EL3_FIRST_NS. Instead introduce an internal macro FFH_SUPPORT which gets enabled when platforms wants to enable lower EL EA handling at EL3. The internal macro FFH_SUPPORT will be automatically enabled if HANDLE_EA_EL3_FIRST_NS is enabled. FFH_SUPPORT along with ENABLE_FEAT_RAS will be used in source files to provide equivalent check which was provided by RAS_FFH_SUPPORT earlier. In generic code we needed a macro which could abstract both HANDLE_EA_EL3_FIRST_NS and RAS_FFH_SUPPORT macros that had limitations. Former was tied up with NS world only while the latter was tied to RAS feature.
This is to allow Secure/Realm world to have their own FFH macros in future.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Ie5692ccbf462f5dcc3f005a5beea5aa35124ac73
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| #
4bd8c929 |
| 09-May-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes I1bfa797e,I0ec7a70e into integration
* changes: fix(tree): correct some typos fix(rockchip): use semicolon instead of comma
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| #
269f3dae |
| 09-May-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "mp/feat_ras" into integration
* changes: refactor(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED refactor(ras): replace RAS_EXTENSION with FEAT_RAS
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| #
1b491eea |
| 13-Feb-2023 |
Elyes Haouas <ehaouas@noos.fr> |
fix(tree): correct some typos
found using codespell (https://github.com/codespell-project/codespell).
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6
fix(tree): correct some typos
found using codespell (https://github.com/codespell-project/codespell).
Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: I1bfa797e3460adddeefa916bb68e22beddaf6373
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| #
9202d519 |
| 13-Feb-2023 |
Manish Pandey <manish.pandey2@arm.com> |
refactor(ras): replace RAS_EXTENSION with FEAT_RAS
The current usage of RAS_EXTENSION in TF-A codebase is to cater for two things in TF-A : 1. Pull in necessary framework and platform hooks for Firm
refactor(ras): replace RAS_EXTENSION with FEAT_RAS
The current usage of RAS_EXTENSION in TF-A codebase is to cater for two things in TF-A : 1. Pull in necessary framework and platform hooks for Firmware first handling(FFH) of RAS errors. 2. Manage the FEAT_RAS extension when switching the worlds.
FFH means that all the EAs from NS are trapped in EL3 first and signaled to NS world later after the first handling is done in firmware. There is an alternate way of handling RAS errors viz Kernel First handling(KFH). Tying FEAT_RAS to RAS_EXTENSION build flag was not correct as the feature is needed for proper handling KFH in as well.
This patch breaks down the RAS_EXTENSION flag into a flag to denote the CPU architecture `ENABLE_FEAT_RAS` which is used in context management during world switch and another flag `RAS_FFH_SUPPORT` to pull in required framework and platform hooks for FFH.
Proper support for KFH will be added in future patches.
BREAKING CHANGE: The previous RAS_EXTENSION is now deprecated. The equivalent functionality can be achieved by the following 2 options: - ENABLE_FEAT_RAS - RAS_FFH_SUPPORT
Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: I1abb9ab6622b8f1b15712b12f17612804d48a6ec
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| #
66a387d4 |
| 23-Feb-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix: remove useless "return" at void functions" into integration
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| #
af4d8c6d |
| 13-Feb-2023 |
Elyes Haouas <ehaouas@noos.fr> |
fix: remove useless "return" at void functions
void functions() returns nothing. So remove useless "return".
found using checkpatch.pl[1]
[1]: https://review.coreboot.org/plugins/gitiles/coreboot/
fix: remove useless "return" at void functions
void functions() returns nothing. So remove useless "return".
found using checkpatch.pl[1]
[1]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/util/lint/checkpatch.pl
Change-Id: I3daab2abec225a657af48f7d8c215cc554713074 Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
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| #
91e52cf0 |
| 22-Mar-2022 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(tegra194/ras): remove incorrect erxctlr assert" into integration
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| #
e272c61c |
| 23-Jul-2021 |
Varun Wadekar <vwadekar@nvidia.com> |
fix(tegra194/ras): remove incorrect erxctlr assert
The ERXCTLR_EL1 register reads are RES0 for some error records leading to a false assert on a read back.
This patch removes the assert on reading
fix(tegra194/ras): remove incorrect erxctlr assert
The ERXCTLR_EL1 register reads are RES0 for some error records leading to a false assert on a read back.
This patch removes the assert on reading back the ERXCTLR_EL1 register to fix this issue.
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Change-Id: I0cab30b12656a800ba87b8bb94b4c67a2331dee6
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| #
28623c10 |
| 08-Nov-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix: libc: use long for 64-bit types on aarch64" into integration
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| #
4ce3e99a |
| 25-Aug-2020 |
Scott Branden <scott.branden@broadcom.com> |
fix: libc: use long for 64-bit types on aarch64
Use long instead of long long on aarch64 for 64_t stdint types. Introduce inttypes.h to properly support printf format specifiers for fixed width type
fix: libc: use long for 64-bit types on aarch64
Use long instead of long long on aarch64 for 64_t stdint types. Introduce inttypes.h to properly support printf format specifiers for fixed width types for such change.
Change-Id: I0bca594687a996fde0a9702d7a383055b99f10a1 Signed-off-by: Scott Branden <scott.branden@broadcom.com>
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485d1f80 |
| 16-Aug-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "refactor(plat/ea_handler): Use default ea handler implementation for panic" into integration
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| #
30e8fa7e |
| 21-Jun-2021 |
Pali Rohár <pali@kernel.org> |
refactor(plat/ea_handler): Use default ea handler implementation for panic
Put default ea handler implementation into function plat_default_ea_handler() which just print verbose information and pani
refactor(plat/ea_handler): Use default ea handler implementation for panic
Put default ea handler implementation into function plat_default_ea_handler() which just print verbose information and panic, so it can be called also from overwritten / weak function plat_ea_handler() implementation.
Replace every custom implementation of printing verbose error message of external aborts in custom plat_ea_handler() functions by a common implementation from plat_default_ea_handler() function.
Signed-off-by: Pali Rohár <pali@kernel.org> Change-Id: I15897f61b62b4c3c29351e693f51d4df381f3b98
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| #
859df7d5 |
| 28-Aug-2020 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "tegra-downstream-08252020" into integration
* changes: Tegra194: remove unused tegra_mc_defs header Tegra: memctrl: platform setup handler functions Tegra194: memctrl
Merge changes from topic "tegra-downstream-08252020" into integration
* changes: Tegra194: remove unused tegra_mc_defs header Tegra: memctrl: platform setup handler functions Tegra194: memctrl: remove streamid security cfg registers Tegra194: memctrl: remove streamid override cfg registers Tegra: debug prints indicating SC7 entry sequence completion Tegra194: add strict checking mode verification Tegra194: memctrl: update TZDRAM base at 1MB granularity Tegra194: ras: split up RAS error clear SMC call. Tegra: platform specific GIC sources Tegra194: add memory barriers during DRAM to SysRAM copy Tegra: sip: add VPR resize enabled check Tegra194: add redundancy checks for MMIO writes Tegra: remove unused cortex_a53.h Tegra194: report failure to enable dual execution Tegra194: verify firewall settings before resource use
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| #
ebd720d0 |
| 07-Jun-2019 |
David Pu <dpu@nvidia.com> |
Tegra194: ras: split up RAS error clear SMC call.
In order to make sure SMC call is within 25us, this patch reduces number of RAS errors accessed to 8 at most for each SMC call and takes a input/out
Tegra194: ras: split up RAS error clear SMC call.
In order to make sure SMC call is within 25us, this patch reduces number of RAS errors accessed to 8 at most for each SMC call and takes a input/output parameter to specify in progress RAS error record index.
The measured SMC call latency is about 20us under Linux test kernel driver.
Change-Id: Ia1b57c8673e0193dc341a36af0b5c09fb48f965f Signed-off-by: David Pu <dpu@nvidia.com>
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| #
5eeb091a |
| 16-Jun-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "tegra194-ras-handling" into integration
* changes: Tegra194: ras: verbose prints for SErrors Prevent RAS register access from lower ELs Tegra194: SiP: clear RAS corre
Merge changes from topic "tegra194-ras-handling" into integration
* changes: Tegra194: ras: verbose prints for SErrors Prevent RAS register access from lower ELs Tegra194: SiP: clear RAS corrected error records Tegra194: add RAS exception handling
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| #
fba5cdc6 |
| 17-May-2019 |
David Pu <dpu@nvidia.com> |
Tegra194: ras: verbose prints for SErrors
This patch provides verbose prints for RAS SErrors handled by the firmware, for improved debugging.
Change-Id: Iaad8d183054d884f606dc4621da2cc6b2375bcf9 Si
Tegra194: ras: verbose prints for SErrors
This patch provides verbose prints for RAS SErrors handled by the firmware, for improved debugging.
Change-Id: Iaad8d183054d884f606dc4621da2cc6b2375bcf9 Signed-off-by: David Pu <dpu@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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| #
0d851195 |
| 21-Mar-2019 |
Varun Wadekar <vwadekar@nvidia.com> |
Tegra194: SiP: clear RAS corrected error records
This patch introduces a function ID to clear all the RAS error records for corrected errors.
Per latest requirement, ARM RAS corrected errors will b
Tegra194: SiP: clear RAS corrected error records
This patch introduces a function ID to clear all the RAS error records for corrected errors.
Per latest requirement, ARM RAS corrected errors will be reported to lower ELs via interrupts and cleared via SMC. This patch provides required function to clear RAS error status.
This patch also sets up all required RAS Corrected errors in order to route RAS corrected errors to lower ELs.
Change-Id: I554ba1d0797b736835aa27824782703682c91e51 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Signed-off-by: David Pu <dpu@nvidia.com>
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| #
8ca61538 |
| 18-Mar-2019 |
David Pu <dpu@nvidia.com> |
Tegra194: add RAS exception handling
This patch adds all Tegra194 RAS nodes definitions and support to handle all uncorrectable RAS errors.
Change-Id: I109b5a8dbca91d92752dc282c4ca30f273c475f9 Sign
Tegra194: add RAS exception handling
This patch adds all Tegra194 RAS nodes definitions and support to handle all uncorrectable RAS errors.
Change-Id: I109b5a8dbca91d92752dc282c4ca30f273c475f9 Signed-off-by: David Pu <dpu@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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