1*292ffc06SSumit Garg /* 2*292ffc06SSumit Garg * Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries. 3*292ffc06SSumit Garg * 4*292ffc06SSumit Garg * SPDX-License-Identifier: BSD-3-Clause 5*292ffc06SSumit Garg */ 6*292ffc06SSumit Garg #include <stddef.h> 7*292ffc06SSumit Garg 8*292ffc06SSumit Garg #include <drivers/qti/accesscontrol/xpu.h> 9*292ffc06SSumit Garg #include <lib/mmio.h> 10*292ffc06SSumit Garg 11*292ffc06SSumit Garg struct RGPartitionRangeType { 12*292ffc06SSumit Garg uint32_t rg_num; 13*292ffc06SSumit Garg uintptr_t start_addr; 14*292ffc06SSumit Garg uintptr_t end_addr; 15*292ffc06SSumit Garg }; 16*292ffc06SSumit Garg 17*292ffc06SSumit Garg struct xpuInstanceType { 18*292ffc06SSumit Garg uintptr_t xpu_base_addr; 19*292ffc06SSumit Garg uint64_t owner_arr_size; 20*292ffc06SSumit Garg void *rg_owner; 21*292ffc06SSumit Garg uint64_t part_range_arr_size; 22*292ffc06SSumit Garg struct RGPartitionRangeType *partition_range; 23*292ffc06SSumit Garg int xpu_id; 24*292ffc06SSumit Garg uint32_t flag; 25*292ffc06SSumit Garg }; 26*292ffc06SSumit Garg 27*292ffc06SSumit Garg #ifdef QTISECLIB_PATH 28*292ffc06SSumit Garg extern struct xpuInstanceType msm_xpu_cfg[]; 29*292ffc06SSumit Garg extern uint32_t msm_xpu_cfg_count; 30*292ffc06SSumit Garg #else 31*292ffc06SSumit Garg static struct xpuInstanceType msm_xpu_cfg[0]; 32*292ffc06SSumit Garg static uint32_t msm_xpu_cfg_count; 33*292ffc06SSumit Garg #endif 34*292ffc06SSumit Garg qti_msm_xpu_bypass(void)35*292ffc06SSumit Gargvoid qti_msm_xpu_bypass(void) 36*292ffc06SSumit Garg { 37*292ffc06SSumit Garg for (int i = 0; i < msm_xpu_cfg_count; i++) { 38*292ffc06SSumit Garg struct xpuInstanceType *xpu = &msm_xpu_cfg[i]; 39*292ffc06SSumit Garg 40*292ffc06SSumit Garg for (int j = 0; j < xpu->part_range_arr_size; j++) { 41*292ffc06SSumit Garg xpu->partition_range[j].start_addr = 0xffffffff; 42*292ffc06SSumit Garg xpu->partition_range[j].end_addr = 0xffffffff; 43*292ffc06SSumit Garg } 44*292ffc06SSumit Garg } 45*292ffc06SSumit Garg } 46