148 	unsigned int i, j;  in apd_io_pad_off()  local
152 		for (j = 0; j < iomuxc_sections[i].reg_num; j++) {  in apd_io_pad_off()
153 			mmio_write_32(iomuxc_sections[i].offset + j * 4, 0);  in apd_io_pad_off()
163 	unsigned int i, j;  in iomuxc_save()  local
167 		for (j = 0U; j < iomuxc_sections[i].reg_num; j++) {  in iomuxc_save()
168 			iomuxc_ctx[index++] = mmio_read_32(iomuxc_sections[i].offset + j * 4);  in iomuxc_save()
177 	unsigned int i, j;  in iomuxc_restore()  local
181 		for (j = 0U; j < iomuxc_sections[i].reg_num; j++) {  in iomuxc_restore()
182 			mmio_write_32(iomuxc_sections[i].offset + j * 4, iomuxc_ctx[index++]);  in iomuxc_restore()
189 	unsigned int i, j;  in gpio_save()  local
193 		for (j = 0U; j < GPIO_CTRL_REG_NUM; j++) {  in gpio_save()
194 			if (j < 4U) {  in gpio_save()
195 				ctx->port_ctrl[j] = mmio_read_32(ctx->base + gpio_ctrl_offset[j]);  in gpio_save()
200 				mmio_write_32(ctx->base + gpio_ctrl_offset[j], 0x0);  in gpio_save()
202 				ctx->port_ctrl[j] = mmio_read_32(ctx->base + gpio_ctrl_offset[j]);  in gpio_save()
206 		for (j = 0U; j < ctx->pin_num; j++) {  in gpio_save()
207 			ctx->gpio_icr[j] = mmio_read_32(ctx->base + 0x80 + j * 4);  in gpio_save()
216 	unsigned int i, j;  in gpio_restore()  local
219 		for (j = 0U; j < ctx->pin_num; j++)  in gpio_restore()
220 			mmio_write_32(ctx->base + 0x80 + j * 4, ctx->gpio_icr[j]);  in gpio_restore()
222 		for (j = 4U; j < GPIO_CTRL_REG_NUM; j++) {  in gpio_restore()
223 			mmio_write_32(ctx->base + gpio_ctrl_offset[j], ctx->port_ctrl[j]);  in gpio_restore()
227 		for (j = 0U; j < 4; j++) {  in gpio_restore()
228 			mmio_write_32(ctx->base + gpio_ctrl_offset[j], ctx->port_ctrl[j]);  in gpio_restore()