| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/ |
| H A D | mt_spm_hwreq.c | 46 static uint32_t spm_hwcg_ctrl_get(struct spm_hwcg_info *info, in spm_hwcg_ctrl_get() argument 51 if (!info) in spm_hwcg_ctrl_get() 56 reg = info->pwr; in spm_hwcg_ctrl_get() 59 reg = info->pwr_msb; in spm_hwcg_ctrl_get() 62 reg = info->module_busy; in spm_hwcg_ctrl_get() 68 static void __spm_hwcg_ctrl(struct spm_hwcg_info *info, in __spm_hwcg_ctrl() argument 74 reg = spm_hwcg_ctrl_get(info, type); in __spm_hwcg_ctrl() 88 struct spm_hwcg_info info; in spm_hwcg_ctrl() local 91 DECLARE_HWCG_REG(DDREN, info); in spm_hwcg_ctrl() 93 DECLARE_HWCG_REG(VRF18, info); in spm_hwcg_ctrl() [all …]
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/ |
| H A D | mt_spm_hwreq.c | 46 static uint32_t spm_hwcg_ctrl_get(struct spm_hwcg_info *info, in spm_hwcg_ctrl_get() argument 51 if (!info) in spm_hwcg_ctrl_get() 56 reg = info->pwr; in spm_hwcg_ctrl_get() 59 reg = info->pwr_msb; in spm_hwcg_ctrl_get() 62 reg = info->module_busy; in spm_hwcg_ctrl_get() 68 static void __spm_hwcg_ctrl(struct spm_hwcg_info *info, in __spm_hwcg_ctrl() argument 74 reg = spm_hwcg_ctrl_get(info, type); in __spm_hwcg_ctrl() 88 struct spm_hwcg_info info; in spm_hwcg_ctrl() local 91 DECLARE_HWCG_REG(DDREN, info); in spm_hwcg_ctrl() 93 DECLARE_HWCG_REG(VRF18, info); in spm_hwcg_ctrl() [all …]
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| /rk3399_ARM-atf/common/ |
| H A D | image_decompress.c | 28 void image_decompress_prepare(struct image_info *info) in image_decompress_prepare() argument 36 saved_image_info = *info; in image_decompress_prepare() 37 info->image_base = decompressor_buf_base; in image_decompress_prepare() 38 info->image_max_size = decompressor_buf_size; in image_decompress_prepare() 41 int image_decompress(struct image_info *info) in image_decompress() argument 51 compressed_image_size = info->image_size; in image_decompress() 52 compressed_image_base = info->image_base; in image_decompress() 53 *info = saved_image_info; in image_decompress() 57 image_base = info->image_base; in image_decompress() 67 &image_base, info->image_max_size, in image_decompress() [all …]
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| /rk3399_ARM-atf/drivers/brcm/i2c/ |
| H A D | i2c.c | 221 static void iproc_i2c_write_trans_data(struct iproc_xact_info *info) in iproc_i2c_write_trans_data() argument 230 __func__, info->devaddr, info->cmd_valid, info->command, in iproc_i2c_write_trans_data() 231 info->size, info->smb_proto); in iproc_i2c_write_trans_data() 234 devaddr = (info->devaddr << 1); in iproc_i2c_write_trans_data() 241 switch (info->smb_proto) { in iproc_i2c_write_trans_data() 244 iproc_i2c_reg_write(info->bus_id, SMB_MSTRDATAWR_REG, in iproc_i2c_write_trans_data() 248 num_data_bytes = info->size; in iproc_i2c_write_trans_data() 249 iproc_i2c_reg_write(info->bus_id, SMB_MSTRDATAWR_REG, in iproc_i2c_write_trans_data() 256 iproc_i2c_reg_write(info->bus_id, SMB_MSTRDATAWR_REG, in iproc_i2c_write_trans_data() 260 iproc_i2c_reg_write(info->bus_id, SMB_MSTRDATAWR_REG, in iproc_i2c_write_trans_data() [all …]
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| /rk3399_ARM-atf/plat/rockchip/common/scmi/ |
| H A D | rockchip_common_clock.c | 61 sel = mmio_read_32(clock->info[MUX_ADDR_INFO]) >> in clk_scmi_common_get_rate() 62 clock->info[MUX_SHIFT_INFO]; in clk_scmi_common_get_rate() 63 sel = sel & (BIT(clock->info[MUX_WIDTH_INFO]) - 1); in clk_scmi_common_get_rate() 64 div = mmio_read_32(clock->info[DIV_ADDR_INFO]) >> in clk_scmi_common_get_rate() 65 clock->info[DIV_SHIFT_INFO]; in clk_scmi_common_get_rate() 66 div = div & (BIT(clock->info[DIV_WIDTH_INFO]) - 1); in clk_scmi_common_get_rate() 78 (clock->info[MUX_WIDTH_INFO] == 0 && clock->info[DIV_WIDTH_INFO] == 0)) in clk_scmi_common_set_rate() 81 sel_mask = BIT(clock->info[MUX_WIDTH_INFO]) - 1; in clk_scmi_common_set_rate() 82 div_mask = BIT(clock->info[DIV_WIDTH_INFO]) - 1; in clk_scmi_common_set_rate() 83 if (clock->info[MUX_WIDTH_INFO] == 0) { in clk_scmi_common_set_rate() [all …]
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| /rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv5_4/ |
| H A D | mt_lp_irqremain.c | 38 const struct mt_lp_irqinfo *info) in mt_lp_irqremain_set() argument 42 if (p_irqs || !info) in mt_lp_irqremain_set() 48 remain_irqs.irqs[idx] = info->val; in mt_lp_irqremain_set() 51 remain_irqs.wakeupsrc_cat[idx] = info->val; in mt_lp_irqremain_set() 54 remain_irqs.wakeupsrc[idx] = info->val; in mt_lp_irqremain_set() 61 struct mt_lp_irqinfo *info) in mt_lp_irqremain_get() argument 63 if (!p_irqs || !info || (idx > remain_irqs.count)) in mt_lp_irqremain_get() 68 info->val = remain_irqs.irqs[idx]; in mt_lp_irqremain_get() 71 info->val = remain_irqs.wakeupsrc_cat[idx]; in mt_lp_irqremain_get() 74 info->val = remain_irqs.wakeupsrc[idx]; in mt_lp_irqremain_get()
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| /rk3399_ARM-atf/plat/nxp/soc-lx2160a/lx2160ardb/ |
| H A D | ddr_init.c | 168 struct ddr_info info; in init_ddr() local 181 zeromem(&info, sizeof(info)); in init_ddr() 184 info.num_ctlrs = NUM_OF_DDRC; in init_ddr() 185 info.spd_addr = spd_addr; in init_ddr() 186 info.ddr[0] = (void *)NXP_DDR_ADDR; in init_ddr() 187 info.ddr[1] = (void *)NXP_DDR2_ADDR; in init_ddr() 188 info.phy[0] = (void *)NXP_DDR_PHY1_ADDR; in init_ddr() 189 info.phy[1] = (void *)NXP_DDR_PHY2_ADDR; in init_ddr() 190 info.clk = get_ddr_freq(&sys, 0); in init_ddr() 191 info.img_loadr = load_img; in init_ddr() [all …]
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| /rk3399_ARM-atf/plat/nxp/soc-ls1088a/ls1088aqds/ |
| H A D | ddr_init.c | 60 struct ddr_info info; in init_ddr() local 69 zeromem(&info, sizeof(struct ddr_info)); in init_ddr() 70 info.num_ctlrs = NUM_OF_DDRC; in init_ddr() 71 info.dimm_on_ctlr = DDRC_NUM_DIMM; in init_ddr() 72 info.clk = get_ddr_freq(&sys, 0); in init_ddr() 73 info.spd_addr = spd_addr; in init_ddr() 74 info.ddr[0] = (void *)NXP_DDR_ADDR; in init_ddr() 76 dram_size = dram_init(&info); in init_ddr()
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| /rk3399_ARM-atf/plat/nxp/soc-ls1046a/ls1046aqds/ |
| H A D | ddr_init.c | 60 struct ddr_info info; in init_ddr() local 73 zeromem(&info, sizeof(struct ddr_info)); in init_ddr() 74 info.num_ctlrs = 1; in init_ddr() 75 info.dimm_on_ctlr = 1; in init_ddr() 76 info.clk = get_ddr_freq(&sys, 0); in init_ddr() 77 info.spd_addr = spd_addr; in init_ddr() 78 info.ddr[0] = (void *)NXP_DDR_ADDR; in init_ddr() 80 dram_size = dram_init(&info); in init_ddr()
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| /rk3399_ARM-atf/plat/nxp/soc-ls1088a/ls1088ardb/ |
| H A D | ddr_init.c | 61 struct ddr_info info; in init_ddr() local 70 zeromem(&info, sizeof(struct ddr_info)); in init_ddr() 71 info.num_ctlrs = NUM_OF_DDRC; in init_ddr() 72 info.dimm_on_ctlr = DDRC_NUM_DIMM; in init_ddr() 73 info.clk = get_ddr_freq(&sys, 0); in init_ddr() 74 info.spd_addr = spd_addr; in init_ddr() 75 info.ddr[0] = (void *)NXP_DDR_ADDR; in init_ddr() 77 dram_size = dram_init(&info); in init_ddr()
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| /rk3399_ARM-atf/drivers/arm/css/scmi/ |
| H A D | scmi_common.c | 37 ((mailbox_mem_t *)(ch->info->scmi_mbx_mem))->status)); in scmi_get_channel() 45 mailbox_mem_t *mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_send_sync_command() 56 ch->info->ring_doorbell(ch->info); in scmi_send_sync_command() 65 if (ch->info->delay != 0) in scmi_send_sync_command() 66 udelay(ch->info->delay); in scmi_send_sync_command() 84 ((mailbox_mem_t *)(ch->info->scmi_mbx_mem))->status)); in scmi_put_channel() 104 mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_proto_version() 137 mbx_mem = (mailbox_mem_t *)(ch->info->scmi_mbx_mem); in scmi_proto_msg_attr() 165 assert(ch && ch->info); in scmi_init() 166 assert(ch->info->db_reg_addr); in scmi_init() [all …]
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| /rk3399_ARM-atf/drivers/brcm/ |
| H A D | spi_flash.c | 56 const struct spi_flash_info *info; in spi_flash_read_id() local 66 for (info = spi_flash_ids; info->name != NULL; info++) { in spi_flash_read_id() 67 if (info->id_len) { in spi_flash_read_id() 68 if (!memcmp(info->id, id, info->id_len)) in spi_flash_read_id() 69 return info; in spi_flash_read_id() 278 const struct spi_flash_info *info = NULL; in spi_flash_probe() local 288 info = spi_flash_read_id(); in spi_flash_probe() 289 if (!info) in spi_flash_probe() 293 info->name, info->n_sectors, in spi_flash_probe() 294 info->sector_size); in spi_flash_probe() [all …]
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| /rk3399_ARM-atf/include/lib/extensions/ |
| H A D | ras.h | 88 typedef int (*err_record_probe_t)(const struct err_record_info *info, 115 typedef int (*err_record_handler_t)(const struct err_record_info *info, 178 static inline int ras_err_ser_probe_memmap(const struct err_record_info *info, in ras_err_ser_probe_memmap() argument 181 assert(info->version == ERR_HANDLER_VERSION); in ras_err_ser_probe_memmap() 183 return ser_probe_memmap(info->memmap.base_addr, info->memmap.size_num_k, in ras_err_ser_probe_memmap() 187 static inline int ras_err_ser_probe_sysreg(const struct err_record_info *info, in ras_err_ser_probe_sysreg() argument 190 assert(info->version == ERR_HANDLER_VERSION); in ras_err_ser_probe_sysreg() 192 return ser_probe_sysreg(info->sysreg.idx_start, info->sysreg.num_idx, in ras_err_ser_probe_sysreg()
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| /rk3399_ARM-atf/drivers/st/ddr/ |
| H A D | stm32mp1_ram.c | 82 ret = stm32mp_ddr_dt_get_info(fdt, node, &config.info); in stm32mp1_ddr_setup() 100 priv->info.size = config.info.size; in stm32mp1_ddr_setup() 103 (uint32_t)priv->info.base, (uint32_t)priv->info.size); in stm32mp1_ddr_setup() 116 uret = stm32mp_ddr_test_addr_bus(config.info.size); in stm32mp1_ddr_setup() 124 if (retsize < config.info.size) { in stm32mp1_ddr_setup() 126 retsize, config.info.size); in stm32mp1_ddr_setup() 150 priv->info.base = STM32MP_DDR_BASE; in stm32mp1_ddr_probe() 151 priv->info.size = 0; in stm32mp1_ddr_probe()
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| H A D | stm32mp_ram.c | 17 int stm32mp_ddr_dt_get_info(void *fdt, int node, struct stm32mp_ddr_info *info) in stm32mp_ddr_dt_get_info() argument 21 ret = fdt_read_uint32(fdt, node, "st,mem-speed", &info->speed); in stm32mp_ddr_dt_get_info() 26 info->size = dt_get_ddr_size(); in stm32mp_ddr_dt_get_info() 27 if (info->size == 0U) { in stm32mp_ddr_dt_get_info() 31 info->name = fdt_getprop(fdt, node, "st,mem-name", NULL); in stm32mp_ddr_dt_get_info() 32 if (info->name == NULL) { in stm32mp_ddr_dt_get_info() 37 INFO("RAM: %s\n", info->name); in stm32mp_ddr_dt_get_info()
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| H A D | stm32mp2_ram.c | 98 ret = stm32mp_ddr_dt_get_info(fdt, node, &config.info); in stm32mp2_ddr_setup() 131 priv->info.size = config.info.size; in stm32mp2_ddr_setup() 133 VERBOSE("%s : ram size(%lx, %lx)\n", __func__, priv->info.base, priv->info.size); in stm32mp2_ddr_setup() 154 uret = stm32mp_ddr_test_addr_bus(config.info.size); in stm32mp2_ddr_setup() 161 if (retsize < config.info.size) { in stm32mp2_ddr_setup() 163 retsize, config.info.size); in stm32mp2_ddr_setup() 203 priv->info.base = STM32MP_DDR_BASE; in stm32mp2_ddr_probe() 204 priv->info.size = 0; in stm32mp2_ddr_probe()
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| /rk3399_ARM-atf/plat/rpi/rpi3/ |
| H A D | rpi3_bl1_setup.c | 83 const char __unused *model, __unused *info; in bl1_platform_setup() local 88 info = "(1GB, Sony, UK)"; in bl1_platform_setup() 92 info = "(1GB, Embest, China)"; in bl1_platform_setup() 96 info = "(1GB, Sony, UK)"; in bl1_platform_setup() 100 info = "(Unknown)"; in bl1_platform_setup() 105 NOTICE("rpi3: Detected: %s %s [0x%08x]\n", model, info, rev); in bl1_platform_setup()
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| /rk3399_ARM-atf/drivers/io/ |
| H A D | io_mtd.c | 89 dev_info_pool[index].info = (uintptr_t)&state_pool[index]; in allocate_dev_info() 102 state = (mtd_dev_state_t *)dev_info->info; in free_dev_info() 140 assert((dev_info->info != 0UL) && (entity->info == 0UL)); in mtd_open() 143 cur = (mtd_dev_state_t *)dev_info->info; in mtd_open() 144 entity->info = (uintptr_t)cur; in mtd_open() 166 assert((entity->info != (uintptr_t)NULL) && (offset >= 0)); in mtd_seek() 168 cur = (mtd_dev_state_t *)entity->info; in mtd_seek() 210 assert(entity->info != (uintptr_t)NULL); in mtd_read() 213 cur = (mtd_dev_state_t *)entity->info; in mtd_read() 237 entity->info = (uintptr_t)NULL; in mtd_close() [all …]
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| /rk3399_ARM-atf/plat/nxp/soc-lx2160a/lx2160aqds/ |
| H A D | ddr_init.c | 303 struct ddr_info info; in init_ddr() local 316 zeromem(&info, sizeof(info)); in init_ddr() 319 info.num_ctlrs = NUM_OF_DDRC; in init_ddr() 320 info.spd_addr = spd_addr; in init_ddr() 321 info.ddr[0] = (void *)NXP_DDR_ADDR; in init_ddr() 322 info.ddr[1] = (void *)NXP_DDR2_ADDR; in init_ddr() 323 info.phy[0] = (void *)NXP_DDR_PHY1_ADDR; in init_ddr() 324 info.phy[1] = (void *)NXP_DDR_PHY2_ADDR; in init_ddr() 325 info.clk = get_ddr_freq(&sys, 0); in init_ddr() 326 info.img_loadr = load_img; in init_ddr() [all …]
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| /rk3399_ARM-atf/plat/nxp/soc-lx2160a/lx2162aqds/ |
| H A D | ddr_init.c | 303 struct ddr_info info; in init_ddr() local 316 zeromem(&info, sizeof(info)); in init_ddr() 319 info.num_ctlrs = NUM_OF_DDRC; in init_ddr() 320 info.spd_addr = spd_addr; in init_ddr() 321 info.ddr[0] = (void *)NXP_DDR_ADDR; in init_ddr() 322 info.ddr[1] = (void *)NXP_DDR2_ADDR; in init_ddr() 323 info.phy[0] = (void *)NXP_DDR_PHY1_ADDR; in init_ddr() 324 info.phy[1] = (void *)NXP_DDR_PHY2_ADDR; in init_ddr() 325 info.clk = get_ddr_freq(&sys, 0); in init_ddr() 326 info.img_loadr = load_img; in init_ddr() [all …]
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| /rk3399_ARM-atf/plat/xilinx/common/ |
| H A D | plat_console.c | 159 static int32_t fdt_add_uart_info(dt_uart_info_t *info, int node, void *dtb) in fdt_add_uart_info() argument 168 strlcpy(info->compatible, com, sizeof(info->compatible)); in fdt_add_uart_info() 182 if (strncmp(info->compatible, DT_UART_DCC_COMPAT, strlen(DT_UART_DCC_COMPAT)) != 0) { in fdt_add_uart_info() 185 info->base = base_addr; in fdt_add_uart_info() 192 info->baud_rate = get_baudrate(dtb); in fdt_add_uart_info() 194 if (strncmp(info->compatible, DT_UART_CAD_COMPAT, in fdt_add_uart_info() 196 info->console_type = CONSOLE_CDNS; in fdt_add_uart_info() 197 } else if (strncmp(info->compatible, DT_UART_PL011_COMPAT, in fdt_add_uart_info() 199 info->console_type = CONSOLE_PL011; in fdt_add_uart_info() 205 info->console_type = CONSOLE_DCC; in fdt_add_uart_info() [all …]
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| /rk3399_ARM-atf/plat/imx/imx8m/ddr/ |
| H A D | ddr4_dvfs.c | 77 void dram_cfg_all_mr(struct dram_info *info, uint32_t pstate) in dram_cfg_all_mr() argument 79 uint32_t num_rank = info->num_rank; in dram_cfg_all_mr() 80 uint32_t dram_type = info->dram_type; in dram_cfg_all_mr() 89 ddr4_mr_write(j, info->mr_table[pstate][j], 0, i, dram_type); in dram_cfg_all_mr() 91 ddr4_mr_write(6, info->mr_table[pstate][7], 0, i, dram_type); in dram_cfg_all_mr() 161 void ddr4_swffc(struct dram_info *info, unsigned int pstate) in ddr4_swffc() argument 163 uint32_t drate = info->timing_info->fsp_table[pstate]; in ddr4_swffc() 233 dram_cfg_all_mr(info, pstate); in ddr4_swffc()
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| /rk3399_ARM-atf/lib/extensions/ras/ |
| H A D | ras_common.c | 69 struct err_record_info *info; in ras_ea_handler() local 81 for_each_err_record_info(i, info) { in ras_ea_handler() 82 assert(info->probe != NULL); in ras_ea_handler() 83 assert(info->handler != NULL); in ras_ea_handler() 87 if (info->probe(info, &probe_data) == 0) in ras_ea_handler() 91 ret = info->handler(info, probe_data, &err_data); in ras_ea_handler()
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| /rk3399_ARM-atf/plat/socionext/synquacer/drivers/scp/ |
| H A D | sq_scp.c | 13 uint32_t sq_scp_get_draminfo(struct draminfo *info) in sq_scp_get_draminfo() argument 16 sq_scmi_get_draminfo(info); in sq_scp_get_draminfo() 18 scpi_get_draminfo(info); in sq_scp_get_draminfo()
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| /rk3399_ARM-atf/plat/marvell/armada/a8k/common/ |
| H A D | plat_pm.c | 507 gpio_info_t *info; in plat_marvell_power_off_gpio() local 515 info = &pm_cfg->cfg.gpio.info[gpio]; in plat_marvell_power_off_gpio() 518 info->cp_index, info->gpio_index)); in plat_marvell_power_off_gpio() 520 info->cp_index, info->gpio_index), in plat_marvell_power_off_gpio() 521 reg & ~MVEBU_GPIO_MASK(info->gpio_index)); in plat_marvell_power_off_gpio() 524 reg = mmio_read_32(MVEBU_PM_MPP_REGS(info->cp_index, in plat_marvell_power_off_gpio() 525 info->gpio_index)); in plat_marvell_power_off_gpio() 526 mmio_write_32(MVEBU_PM_MPP_REGS(info->cp_index, in plat_marvell_power_off_gpio() 527 info->gpio_index), in plat_marvell_power_off_gpio() 528 reg & ~MVEBU_MPP_MASK(info->gpio_index)); in plat_marvell_power_off_gpio() [all …]
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