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72e8f245 |
| 08-Aug-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "chore: update to use Arm word across TF-A" into integration
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4c700c15 |
| 01-Aug-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
chore: update to use Arm word across TF-A
Align entire TF-A to use Arm in copyright header.
Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244 Signed-off-by: Govindraj Raja <govindraj.raja@arm.co
chore: update to use Arm word across TF-A
Align entire TF-A to use Arm in copyright header.
Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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0cd5d1d1 |
| 02-Mar-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "lib/extensions/ras: fix bug of binary search" into integration
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| #
0b1838a9 |
| 22-Apr-2020 |
Heyi Guo <guoheyi@linux.alibaba.com> |
lib/extensions/ras: fix bug of binary search
In ras_interrupt_handler(), binary search end was set to the size of the ras_interrupt_mappings array, which would cause out of bound access when the inp
lib/extensions/ras: fix bug of binary search
In ras_interrupt_handler(), binary search end was set to the size of the ras_interrupt_mappings array, which would cause out of bound access when the input intr_raw is larger than all the elements in ras_interrupt_mappings.
Signed-off-by: Heyi Guo <guoheyi@linux.alibaba.com> Change-Id: Id2cff73177134b09d4d8beb596c3429b98ec5066
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5eeb091a |
| 16-Jun-2020 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "tegra194-ras-handling" into integration
* changes: Tegra194: ras: verbose prints for SErrors Prevent RAS register access from lower ELs Tegra194: SiP: clear RAS corre
Merge changes from topic "tegra194-ras-handling" into integration
* changes: Tegra194: ras: verbose prints for SErrors Prevent RAS register access from lower ELs Tegra194: SiP: clear RAS corrected error records Tegra194: add RAS exception handling
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8ca61538 |
| 18-Mar-2019 |
David Pu <dpu@nvidia.com> |
Tegra194: add RAS exception handling
This patch adds all Tegra194 RAS nodes definitions and support to handle all uncorrectable RAS errors.
Change-Id: I109b5a8dbca91d92752dc282c4ca30f273c475f9 Sign
Tegra194: add RAS exception handling
This patch adds all Tegra194 RAS nodes definitions and support to handle all uncorrectable RAS errors.
Change-Id: I109b5a8dbca91d92752dc282c4ca30f273c475f9 Signed-off-by: David Pu <dpu@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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a8ab58e9 |
| 13-Aug-2019 |
Paul Beesley <paul.beesley@arm.com> |
Merge changes from topic "jc/coverity-fixes" into integration
* changes: Fix Coverity #261967, Infinite loop Fix Coverity #343017, Missing unlock Fix Coverity #343008, Side affect in assertion
Merge changes from topic "jc/coverity-fixes" into integration
* changes: Fix Coverity #261967, Infinite loop Fix Coverity #343017, Missing unlock Fix Coverity #343008, Side affect in assertion Fix Coverity #342970, Uninitialized scalar variable
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dbff5263 |
| 23-Jul-2019 |
Justin Chadwell <justin.chadwell@arm.com> |
Fix Coverity #342970, Uninitialized scalar variable
This ensures that probe_data starts with a reasonable default, as opposed to whatever was left on the stack.
Change-Id: I5550efea5e2bec7717f9fa06
Fix Coverity #342970, Uninitialized scalar variable
This ensures that probe_data starts with a reasonable default, as opposed to whatever was left on the stack.
Change-Id: I5550efea5e2bec7717f9fa063cb11e6a7005cce5 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
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9a207532 |
| 04-Jan-2019 |
Antonio Niño Díaz <antonio.ninodiaz@arm.com> |
Merge pull request #1726 from antonio-nino-diaz-arm/an/includes
Sanitise includes across codebase
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09d40e0e |
| 14-Dec-2018 |
Antonio Nino Diaz <antonio.ninodiaz@arm.com> |
Sanitise includes across codebase
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH} - inclu
Sanitise includes across codebase
Enforce full include path for includes. Deprecate old paths.
The following folders inside include/lib have been left unchanged:
- include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH}
The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them).
For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support").
This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems.
Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged.
Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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7e0a38a4 |
| 04-Oct-2018 |
Soby Mathew <soby.mathew@arm.com> |
Merge pull request #1603 from antonio-nino-diaz-arm/db/reclaim-init
Reclaim BL31 initialization code memory for runtime data
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87c85134 |
| 20-Sep-2018 |
Daniel Boulby <daniel.boulby@arm.com> |
Mark BL31 initialization functions
Mark the initialization functions in BL31, such as context management, EHF, RAS and PSCI as __init so that they can be reclaimed by the platform when no longer nee
Mark BL31 initialization functions
Mark the initialization functions in BL31, such as context management, EHF, RAS and PSCI as __init so that they can be reclaimed by the platform when no longer needed
Change-Id: I7446aeee3dde8950b0f410cb766b7a2312c20130 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
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11dfe0b4 |
| 22-Aug-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1532 from jeenu-arm/misra-fixes
MISRA fixes
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30a8d96e |
| 02-Aug-2018 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
RAS: MISRA fixes
These changes address most of the required MISRA rules. In the process, some from generic code is also fixed.
No functional changes.
Change-Id: I76cacf6e1d73b09510561b5090c2bb66d8
RAS: MISRA fixes
These changes address most of the required MISRA rules. In the process, some from generic code is also fixed.
No functional changes.
Change-Id: I76cacf6e1d73b09510561b5090c2bb66d81bec88 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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eef90a77 |
| 27-Jul-2018 |
Soby Mathew <soby.mathew@arm.com> |
Merge pull request #1497 from SNG-ARM/master
RAS changes for SGI575 platform
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4576f73c |
| 12-May-2018 |
Sughosh Ganu <sughosh.ganu@arm.com> |
RAS: ras_common: Add null pointer check for error record probe function
Add a null pointer check for the error record probe function -- avoids a panic in case a platform has not defined it.
Change-
RAS: ras_common: Add null pointer check for error record probe function
Add a null pointer check for the error record probe function -- avoids a panic in case a platform has not defined it.
Change-Id: I1139fa0df33297a12ec16615cacd07540925f991 Signed-off-by: Sughosh Ganu <sughosh.ganu@arm.com>
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a513506b |
| 15-May-2018 |
Dimitris Papastamos <dimitris.papastamos@arm.com> |
Merge pull request #1373 from jeenu-arm/ras-support
RAS support
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ca6d9185 |
| 12-Dec-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
RAS: Allow individual interrupt registration
EHF currently allows for registering interrupt handlers for a defined priority ranges. This is primarily targeted at various EL3 dispatchers to own range
RAS: Allow individual interrupt registration
EHF currently allows for registering interrupt handlers for a defined priority ranges. This is primarily targeted at various EL3 dispatchers to own ranges of secure interrupt priorities in order to delegate execution to lower ELs.
The RAS support added by earlier patches necessitates registering handlers based on interrupt number so that error handling agents shall receive and handle specific Error Recovery or Fault Handling interrupts at EL3.
This patch introduces a macro, RAS_INTERRUPTS() to declare an array of interrupt numbers and handlers. Error handling agents can use this macro to register handlers for individual RAS interrupts. The array is expected to be sorted in the increasing order of interrupt numbers.
As part of RAS initialisation, the list of all RAS interrupts are sorted based on their ID so that, given an interrupt, its handler can be looked up with a simple binary search.
For an error handling agent that wants to handle a RAS interrupt, platform must:
- Define PLAT_RAS_PRI to be the priority of all RAS exceptions.
- Enumerate interrupts to have the GIC driver program individual EL3 interrupts to the required priority range. This is required by EHF even before this patch.
Documentation to follow.
Change-Id: I9471e4887ff541f8a7a63309e9cd8f771f76aeda Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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| #
362599ec |
| 08-Dec-2017 |
Jeenu Viswambharan <jeenu.viswambharan@arm.com> |
RAS: Add support for node registration
Previous patches added frameworks for handling RAS errors. This patch introduces features that the platform can use to enumerate and iterate RAS nodes:
- Th
RAS: Add support for node registration
Previous patches added frameworks for handling RAS errors. This patch introduces features that the platform can use to enumerate and iterate RAS nodes:
- The REGISTER_RAS_NODES() can be used to expose an array of ras_node_info_t structures. Each ras_node_info_t describes a RAS node, along with handlers for probing the node for error, and if did record an error, another handler to handle it.
- The macro for_each_ras_node() can be used to iterate over the registered RAS nodes, probe for, and handle any errors.
The common platform EA handler has been amended using error handling primitives introduced by both this and previous patches.
Change-Id: I2e13f65a88357bc48cd97d608db6c541fad73853 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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