1*0b0e6766SJiafei Pan /*
2*0b0e6766SJiafei Pan * Copyright 2022 NXP
3*0b0e6766SJiafei Pan *
4*0b0e6766SJiafei Pan * SPDX-License-Identifier: BSD-3-Clause
5*0b0e6766SJiafei Pan */
6*0b0e6766SJiafei Pan
7*0b0e6766SJiafei Pan #include <errno.h>
8*0b0e6766SJiafei Pan
9*0b0e6766SJiafei Pan #include <common/debug.h>
10*0b0e6766SJiafei Pan #include <ddr.h>
11*0b0e6766SJiafei Pan #include <utils.h>
12*0b0e6766SJiafei Pan
13*0b0e6766SJiafei Pan #include <errata.h>
14*0b0e6766SJiafei Pan #include <platform_def.h>
15*0b0e6766SJiafei Pan
16*0b0e6766SJiafei Pan #ifdef CONFIG_STATIC_DDR
17*0b0e6766SJiafei Pan #error No static value defined
18*0b0e6766SJiafei Pan #endif
19*0b0e6766SJiafei Pan
20*0b0e6766SJiafei Pan static const struct rc_timing rce[] = {
21*0b0e6766SJiafei Pan {U(1600), U(8), U(8)},
22*0b0e6766SJiafei Pan {U(1867), U(8), U(8)},
23*0b0e6766SJiafei Pan {U(2134), U(8), U(9)},
24*0b0e6766SJiafei Pan {}
25*0b0e6766SJiafei Pan };
26*0b0e6766SJiafei Pan
27*0b0e6766SJiafei Pan static const struct board_timing udimm[] = {
28*0b0e6766SJiafei Pan {U(0x04), rce, U(0x01020307), U(0x08090b06)},
29*0b0e6766SJiafei Pan };
30*0b0e6766SJiafei Pan
ddr_board_options(struct ddr_info * priv)31*0b0e6766SJiafei Pan int ddr_board_options(struct ddr_info *priv)
32*0b0e6766SJiafei Pan {
33*0b0e6766SJiafei Pan int ret;
34*0b0e6766SJiafei Pan struct memctl_opt *popts = &priv->opt;
35*0b0e6766SJiafei Pan
36*0b0e6766SJiafei Pan if (popts->rdimm != 0) {
37*0b0e6766SJiafei Pan debug("RDIMM parameters not set.\n");
38*0b0e6766SJiafei Pan return -EINVAL;
39*0b0e6766SJiafei Pan }
40*0b0e6766SJiafei Pan
41*0b0e6766SJiafei Pan ret = cal_board_params(priv, udimm, ARRAY_SIZE(udimm));
42*0b0e6766SJiafei Pan if (ret != 0) {
43*0b0e6766SJiafei Pan return ret;
44*0b0e6766SJiafei Pan }
45*0b0e6766SJiafei Pan
46*0b0e6766SJiafei Pan popts->addr_hash = 1;
47*0b0e6766SJiafei Pan popts->cpo_sample = U(0x7b);
48*0b0e6766SJiafei Pan popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
49*0b0e6766SJiafei Pan DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
50*0b0e6766SJiafei Pan popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
51*0b0e6766SJiafei Pan DDR_CDR2_VREF_TRAIN_EN |
52*0b0e6766SJiafei Pan DDR_CDR2_VREF_RANGE_2;
53*0b0e6766SJiafei Pan
54*0b0e6766SJiafei Pan return 0;
55*0b0e6766SJiafei Pan }
56*0b0e6766SJiafei Pan
init_ddr(void)57*0b0e6766SJiafei Pan long long init_ddr(void)
58*0b0e6766SJiafei Pan {
59*0b0e6766SJiafei Pan int spd_addr[] = { NXP_SPD_EEPROM0 };
60*0b0e6766SJiafei Pan struct ddr_info info;
61*0b0e6766SJiafei Pan struct sysinfo sys;
62*0b0e6766SJiafei Pan long long dram_size;
63*0b0e6766SJiafei Pan
64*0b0e6766SJiafei Pan zeromem(&sys, sizeof(sys));
65*0b0e6766SJiafei Pan get_clocks(&sys);
66*0b0e6766SJiafei Pan debug("platform clock %lu\n", sys.freq_platform);
67*0b0e6766SJiafei Pan debug("DDR PLL %lu\n", sys.freq_ddr_pll0);
68*0b0e6766SJiafei Pan
69*0b0e6766SJiafei Pan zeromem(&info, sizeof(struct ddr_info));
70*0b0e6766SJiafei Pan info.num_ctlrs = NUM_OF_DDRC;
71*0b0e6766SJiafei Pan info.dimm_on_ctlr = DDRC_NUM_DIMM;
72*0b0e6766SJiafei Pan info.clk = get_ddr_freq(&sys, 0);
73*0b0e6766SJiafei Pan info.spd_addr = spd_addr;
74*0b0e6766SJiafei Pan info.ddr[0] = (void *)NXP_DDR_ADDR;
75*0b0e6766SJiafei Pan
76*0b0e6766SJiafei Pan dram_size = dram_init(&info);
77*0b0e6766SJiafei Pan if (dram_size < 0) {
78*0b0e6766SJiafei Pan ERROR("DDR init failed.\n");
79*0b0e6766SJiafei Pan }
80*0b0e6766SJiafei Pan
81*0b0e6766SJiafei Pan return dram_size;
82*0b0e6766SJiafei Pan }
83