61 	sel = mmio_read_32(clock->info[MUX_ADDR_INFO]) >>  in clk_scmi_common_get_rate()
62 	      clock->info[MUX_SHIFT_INFO];  in clk_scmi_common_get_rate()
63 	sel = sel & (BIT(clock->info[MUX_WIDTH_INFO]) - 1);  in clk_scmi_common_get_rate()
64 	div = mmio_read_32(clock->info[DIV_ADDR_INFO]) >>  in clk_scmi_common_get_rate()
65 	      clock->info[DIV_SHIFT_INFO];  in clk_scmi_common_get_rate()
66 	div = div & (BIT(clock->info[DIV_WIDTH_INFO]) - 1);  in clk_scmi_common_get_rate()
78 	    (clock->info[MUX_WIDTH_INFO] == 0 && clock->info[DIV_WIDTH_INFO] == 0))  in clk_scmi_common_set_rate()
81 	sel_mask = BIT(clock->info[MUX_WIDTH_INFO]) - 1;  in clk_scmi_common_set_rate()
82 	div_mask = BIT(clock->info[DIV_WIDTH_INFO]) - 1;  in clk_scmi_common_set_rate()
83 	if (clock->info[MUX_WIDTH_INFO] == 0) {  in clk_scmi_common_set_rate()
88 		mmio_write_32(clock->info[DIV_ADDR_INFO],  in clk_scmi_common_set_rate()
90 					      clock->info[DIV_SHIFT_INFO]));  in clk_scmi_common_set_rate()
91 	} else if (clock->info[DIV_WIDTH_INFO] == 0) {  in clk_scmi_common_set_rate()
102 		mmio_write_32(clock->info[MUX_ADDR_INFO],  in clk_scmi_common_set_rate()
104 					      clock->info[MUX_SHIFT_INFO]));  in clk_scmi_common_set_rate()
123 		mmio_write_32(clock->info[DIV_ADDR_INFO],  in clk_scmi_common_set_rate()
125 					      clock->info[DIV_SHIFT_INFO]));  in clk_scmi_common_set_rate()
126 		mmio_write_32(clock->info[MUX_ADDR_INFO],  in clk_scmi_common_set_rate()
128 					      clock->info[MUX_SHIFT_INFO]));  in clk_scmi_common_set_rate()
129 		mmio_write_32(clock->info[DIV_ADDR_INFO],  in clk_scmi_common_set_rate()
131 					      clock->info[DIV_SHIFT_INFO]));  in clk_scmi_common_set_rate()
138 	mmio_write_32(clock->info[GATE_ADDR_INFO],  in clk_scmi_common_set_status()
140 				      clock->info[GATE_SHIFT_INFO]));  in clk_scmi_common_set_status()