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Searched refs:freq (Results 1 – 25 of 47) sorted by relevance

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/rk3399_ARM-atf/drivers/renesas/common/emmc/
H A Demmc_mount.c22 static uint32_t emmc_set_timeout_register_value(uint32_t freq);
24 static uint32_t emmc_calc_tran_speed(uint32_t *freq);
54 uint32_t freq = MMC_400KHZ; /* 390KHz */ in emmc_card_init() local
70 result = emmc_set_request_mmc_clock(&freq); in emmc_card_init()
168 result_calc = emmc_calc_tran_speed(&freq); in emmc_card_init()
174 mmc_drv_obj.max_freq = freq; /* max frequency (card spec) */ in emmc_card_init()
176 result = emmc_set_request_mmc_clock(&freq); in emmc_card_init()
183 mmc_drv_obj.data_timeout = emmc_set_timeout_register_value(freq); in emmc_card_init()
224 uint32_t freq; /* High speed mode clock frequency */ in emmc_high_speed() local
237 freq = MMC_52MHZ; in emmc_high_speed()
[all …]
H A Demmc_utility.c195 uint32_t freq; in emmc_send_idle_cmd() local
219 freq = MMC_400KHZ; in emmc_send_idle_cmd()
220 result = emmc_set_request_mmc_clock(&freq); in emmc_send_idle_cmd()
H A Demmc_def.h40 EMMC_ERROR_CODE emmc_set_request_mmc_clock(uint32_t *freq);
/rk3399_ARM-atf/drivers/renesas/common/delay/
H A Dmicro_delay.c20 uint64_t freq; in rcar_micro_delay() local
25 freq = read_cntfrq_el0(); in rcar_micro_delay()
29 wait_time = ((get_count - base_count) * RCAR_CONV_MICROSEC) / freq; in rcar_micro_delay()
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/apusys/
H A Dapupwr_clkctl.c115 int32_t apupwr_smc_acc_set_parent(uint32_t freq, uint32_t domain) in apupwr_smc_acc_set_parent() argument
121 if (freq > DVFS_FREQ_ACC_APUPLL) { in apupwr_smc_acc_set_parent()
122 ERROR("%s wrong clksrc: %d\n", __func__, freq); in apupwr_smc_acc_set_parent()
143 switch (freq) { in apupwr_smc_acc_set_parent()
192 __func__, freq); in apupwr_smc_acc_set_parent()
200 int32_t apupwr_smc_pll_set_rate(uint32_t freq, bool div2, uint32_t domain) in apupwr_smc_pll_set_rate() argument
205 if (freq > DVFS_FREQ_MAX) { in apupwr_smc_pll_set_rate()
206 ERROR("%s wrong freq: %d\n", __func__, freq); in apupwr_smc_pll_set_rate()
251 anpu_pll_set_rate(domain, PLL_MODE, (div2) ? (freq * 2) : freq); in apupwr_smc_pll_set_rate()
307 __func__, __LINE__, domain, (div2) ? (freq * 2) : freq); in apupwr_smc_pll_set_rate()
H A Dapupwr_clkctl.h15 int32_t apupwr_smc_acc_set_parent(uint32_t freq, uint32_t domain);
22 enum pll_set_rate_mode mode, int32_t freq);
H A Dapupll.c238 static int32_t _cal_pll_data(uint32_t *pd, uint32_t *dds, uint32_t freq) in _cal_pll_data() argument
243 vco = freq; in _cal_pll_data()
508 enum pll_set_rate_mode mode, int32_t freq) in anpu_pll_set_rate() argument
519 _cal_pll_data(&pd, &dds, freq / 1000); in anpu_pll_set_rate()
522 __func__, pllidx2name(pll_idx), pd, dds, freq / 1000, mode); in anpu_pll_set_rate()
/rk3399_ARM-atf/plat/renesas/rcar_gen4/aarch64/
H A Dplatform_common.c89 unsigned int freq; in plat_get_syscnt_freq2() local
91 freq = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); in plat_get_syscnt_freq2()
92 if (freq == 0) in plat_get_syscnt_freq2()
95 return freq; in plat_get_syscnt_freq2()
/rk3399_ARM-atf/plat/arm/board/arm_fpga/
H A Dfpga_bl31_setup.c148 unsigned int freq; in pl011_freq_from_divider() local
150 freq = divider * FPGA_DEFAULT_BAUDRATE * PL011_OVERSAMPLING; in pl011_freq_from_divider()
152 return freq >> PL011_FRAC_SHIFT; in pl011_freq_from_divider()
172 uint32_t freq; in fpga_get_system_frequency() local
174 err = fdt_read_uint32(fdt, node, "clock-frequency", &freq); in fpga_get_system_frequency()
176 return freq; in fpga_get_system_frequency()
218 static void fpga_dtb_update_clock(void *fdt, unsigned int freq) in fpga_dtb_update_clock() argument
220 uint32_t freq_dtb = fdt32_to_cpu(freq); in fpga_dtb_update_clock()
/rk3399_ARM-atf/plat/renesas/rcar_gen5/aarch64/
H A Dplatform_common.c101 unsigned int freq; in plat_get_syscnt_freq2() local
103 freq = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); in plat_get_syscnt_freq2()
104 if (freq == 0U) { in plat_get_syscnt_freq2()
108 return freq; in plat_get_syscnt_freq2()
/rk3399_ARM-atf/fdts/
H A Dfvp-ve-Cortex-A5x1.dts84 freq-range = <50000000 100000000>;
93 freq-range = <5000000 50000000>;
102 freq-range = <80000000 120000000>;
111 freq-range = <23750000 165000000>;
120 freq-range = <80000000 80000000>;
129 freq-range = <25000000 60000000>;
/rk3399_ARM-atf/plat/hisilicon/hikey/
H A Dhisi_dvfs.c41 unsigned int freq; member
48 unsigned int freq; member
55 unsigned int freq; member
234 if (acpu_dvfs_profile[tar_prof].freq > 800000) { in acpu_dvfs_freq_ascend()
387 if (acpu_dvfs_profile[tar_prof].freq > 800000) in acpu_dvfs_freq_ascend()
452 if (acpu_dvfs_profile[tar_prof].freq > 800000) { in acpu_dvfs_freq_descend()
534 if (acpu_dvfs_profile[tar_prof].freq > 800000) in acpu_dvfs_freq_descend()
671 if (max_freq == hi6220_acpu_profile[i].freq) { in acpu_dvfs_set_freq()
H A Dhikey_ddr.c1085 static void ddrc_common_init(int freq) in ddrc_common_init() argument
1108 if (freq == DDR_FREQ_800M) in ddrc_common_init()
1109 mmio_write_32((0xf7128000 + 0x240), 167 * (freq / 2) / 1024); in ddrc_common_init()
1111 mmio_write_32((0xf7128000 + 0x240), 167 * freq / 1024); in ddrc_common_init()
1296 int lpddr3_freq_init(int freq) in lpddr3_freq_init() argument
1300 if (freq > DDR_FREQ_150M) { in lpddr3_freq_init()
1306 if (freq > DDR_FREQ_266M) { in lpddr3_freq_init()
1312 if (freq > DDR_FREQ_400M) { in lpddr3_freq_init()
1318 if (freq > DDR_FREQ_533M) { in lpddr3_freq_init()
1327 static void init_ddr(int freq) in init_ddr() argument
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/rk3399_ARM-atf/drivers/nxp/clk/s32cc/
H A Ds32cc_clk_drv.c607 dc = (uint32_t)(pll_vco / pdiv->freq); in enable_pll_div()
839 unsigned long out = dfs_div->freq; in get_dfs_mfi_mfn()
868 if (ofreq != dfs_div->freq) { in get_dfs_mfi_mfn()
870 dfs_div->freq); in get_dfs_mfi_mfn()
1170 if (cgm_div->freq == 0U) { in enable_cgm_div()
1196 dc64 = ((pfreq * FP_PRECISION) / cgm_div->freq) / FP_PRECISION; in enable_cgm_div()
1199 if ((pfreq / dc64) != cgm_div->freq) { in enable_cgm_div()
1203 cgm_div->freq, (unsigned long)(pfreq / dc)); in enable_cgm_div()
1228 cgm_div->freq = rate; in set_cgm_div_freq()
1290 *rate = cgm_div->freq; in get_cgm_div_freq()
[all …]
/rk3399_ARM-atf/plat/renesas/common/aarch64/
H A Dplatform_common.c211 unsigned int freq; in plat_get_syscnt_freq2() local
213 freq = mmio_read_32(ARM_SYS_CNTCTL_BASE + CNTFID_OFF); in plat_get_syscnt_freq2()
214 if (freq == 0) in plat_get_syscnt_freq2()
217 return freq; in plat_get_syscnt_freq2()
/rk3399_ARM-atf/include/drivers/nxp/clk/s32cc/
H A Ds32cc-clk-modules.h53 unsigned long freq; member
63 .freq = (FREQ), \
120 unsigned long freq; member
161 unsigned long freq; member
295 unsigned long freq; member
/rk3399_ARM-atf/drivers/st/clk/
H A Dstm32mp_clkfunc.c26 int fdt_osc_read_freq(const char *name, uint32_t *freq) in fdt_osc_read_freq() argument
59 *freq = fdt32_to_cpu(*cuint); in fdt_osc_read_freq()
66 *freq = 0; in fdt_osc_read_freq()
/rk3399_ARM-atf/include/drivers/st/
H A Dstm32mp_clkfunc.h16 int fdt_osc_read_freq(const char *name, uint32_t *freq);
/rk3399_ARM-atf/plat/imx/imx7/common/
H A Dimx7_bl2_el3_common.c124 unsigned long freq = SYS_COUNTER_FREQ_IN_TICKS; in imx7_setup_system_counter() local
127 write_cntfrq(freq); in imx7_setup_system_counter()
/rk3399_ARM-atf/drivers/st/mmc/
H A Dstm32_sdmmc2.c174 uint32_t freq = STM32MP_MMC_INIT_FREQ; in stm32_sdmmc2_init() local
179 freq = MIN(sdmmc2_params.max_freq, freq); in stm32_sdmmc2_init()
207 clock_div = div_round_up(sdmmc2_params.clk_rate, freq * 2U); in stm32_sdmmc2_init()
485 uint32_t clock_div, max_freq, freq; in stm32_sdmmc2_set_ios() local
518 freq = MIN(sdmmc2_params.max_freq, max_freq); in stm32_sdmmc2_set_ios()
520 freq = max_freq; in stm32_sdmmc2_set_ios()
523 clock_div = div_round_up(clk_rate, freq * 2U); in stm32_sdmmc2_set_ios()
/rk3399_ARM-atf/plat/mediatek/drivers/spm/
H A Dmt_spm_vcorefs_exp.h15 int spm_vcorefs_get_dram_freq(uint32_t gear, uint32_t *freq);
/rk3399_ARM-atf/drivers/nxp/ddr/nxp-ddr/
H A Dregs.c360 const unsigned int freq = clk / 1000000U; in cal_ddr_sdram_rcw() local
367 rc0a = freq > 3200U ? 7U : in cal_ddr_sdram_rcw()
368 (freq > 2933U ? 6U : in cal_ddr_sdram_rcw()
369 (freq > 2666U ? 5U : in cal_ddr_sdram_rcw()
370 (freq > 2400U ? 4U : in cal_ddr_sdram_rcw()
371 (freq > 2133U ? 3U : in cal_ddr_sdram_rcw()
372 (freq > 1866U ? 2U : in cal_ddr_sdram_rcw()
373 (freq > 1600U ? 1U : 0U)))))); in cal_ddr_sdram_rcw()
374 rc0f = freq > 3200U ? 3U : in cal_ddr_sdram_rcw()
375 (freq > 2400U ? 2U : in cal_ddr_sdram_rcw()
[all …]
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/include/
H A Dmce_private.h159 uint32_t freq,
233 int32_t ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
255 int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable);
/rk3399_ARM-atf/drivers/mentor/i2c/
H A Dmi2cv.c245 unsigned int n, m, freq, margin, min_margin = 0xffffffff; in mentor_i2c_bus_speed_set() local
252 freq = CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n)); in mentor_i2c_bus_speed_set()
253 val = requested_speed - freq; in mentor_i2c_bus_speed_set()
256 if ((freq <= requested_speed) && in mentor_i2c_bus_speed_set()
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/mce/
H A Dnvg.c233 int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable) in nvg_cc3_ctrl() argument
249 val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) | in nvg_cc3_ctrl()

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