| /rk3399_ARM-atf/plat/hisilicon/hikey/ |
| H A D | hikey_ddr.c | 22 unsigned int data; in init_pll() local
24 data = mmio_read_32((0xf7032000 + 0x000)); in init_pll()
25 data |= 0x1; in init_pll()
26 mmio_write_32((0xf7032000 + 0x000), data); in init_pll()
28 data = mmio_read_32((0xf7032000 + 0x000)); in init_pll()
29 } while (!(data & (1 << 28))); in init_pll()
31 data = mmio_read_32((0xf7800000 + 0x000)); in init_pll()
32 data &= ~0x007; in init_pll()
33 data |= 0x004; in init_pll()
34 mmio_write_32((0xf7800000 + 0x000), data); in init_pll()
[all …]
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| H A D | hikey_bl_common.c | 19 uint32_t data; in hikey_sp804_init() local
22 data = mmio_read_32(AO_SC_TIMER_EN0); in hikey_sp804_init()
23 while (data & 3) { in hikey_sp804_init()
24 data &= ~3; in hikey_sp804_init()
25 data |= 3 << 16; in hikey_sp804_init()
26 mmio_write_32(AO_SC_TIMER_EN0, data); in hikey_sp804_init()
27 data = mmio_read_32(AO_SC_TIMER_EN0); in hikey_sp804_init()
30 data = mmio_read_32(AO_SC_PERIPH_CLKSTAT4); in hikey_sp804_init()
31 while (!(data & PCLK_TIMER1) || !(data & PCLK_TIMER0)) { in hikey_sp804_init()
33 data = mmio_read_32(AO_SC_PERIPH_CLKSTAT4); in hikey_sp804_init()
[all …]
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| H A D | hikey_bl2_setup.c | 188 unsigned int data; in reset_dwmmc_clk() local
193 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); in reset_dwmmc_clk()
194 } while (data & PERI_CLK0_MMC0); in reset_dwmmc_clk()
198 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); in reset_dwmmc_clk()
199 } while (!(data & PERI_CLK0_MMC0)); in reset_dwmmc_clk()
204 data = mmio_read_32(PERI_SC_PERIPH_CTRL2); in reset_dwmmc_clk()
205 data |= 3; in reset_dwmmc_clk()
206 mmio_write_32(PERI_SC_PERIPH_CTRL2, data); in reset_dwmmc_clk()
209 data = mmio_read_32(PERI_SC_PERIPH_CTRL13); in reset_dwmmc_clk()
210 data |= 1 << 3; in reset_dwmmc_clk()
[all …]
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| /rk3399_ARM-atf/drivers/marvell/comphy/ |
| H A D | phy-comphy-cp110.c | 305 uint32_t mask, data; in mvebu_cp110_comphy_is_pll_locked() local
314 data = SD_EXTERNAL_STATUS0_PLL_TX_MASK & in mvebu_cp110_comphy_is_pll_locked()
316 mask = data; in mvebu_cp110_comphy_is_pll_locked()
317 data = polling_with_timeout(addr, data, mask, in mvebu_cp110_comphy_is_pll_locked()
319 if (data != 0) { in mvebu_cp110_comphy_is_pll_locked()
320 if (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK) in mvebu_cp110_comphy_is_pll_locked()
322 if (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK) in mvebu_cp110_comphy_is_pll_locked()
335 uint32_t mask, data; in mvebu_cp110_polarity_invert() local
338 data = mask = 0x0U; in mvebu_cp110_polarity_invert()
340 data |= (1 << HPIPE_SYNC_PATTERN_TXD_INV_OFFSET); in mvebu_cp110_polarity_invert()
[all …]
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| H A D | phy-comphy-3700.c | 217 static void comphy_set_indirect(uintptr_t addr, uint32_t offset, uint16_t data, in comphy_set_indirect() argument
235 reg_set(addr + COMPHY_LANE2_INDIR_DATA_OFFSET, data, mask); in comphy_set_indirect()
240 uint16_t data, uint16_t mask) in comphy_sata_set_indirect() argument
242 comphy_set_indirect(addr, reg_offset, data, mask, true); in comphy_sata_set_indirect()
247 uint16_t data, uint16_t mask) in comphy_usb3_set_indirect() argument
249 comphy_set_indirect(addr, reg_offset, data, mask, false); in comphy_usb3_set_indirect()
254 uint16_t data, uint16_t mask) in comphy_usb3_set_direct() argument
256 reg_set16((reg_offset * PHY_SHFT(USB3) + addr), data, mask); in comphy_usb3_set_direct()
291 uint32_t offset, data = 0, ref_clk; in mvebu_a3700_comphy_sata_power_on() local
309 data |= TXD_INVERT_BIT; in mvebu_a3700_comphy_sata_power_on()
[all …]
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| H A D | phy-comphy-common.h | 129 uint32_t data; in polling_with_timeout() local
134 data = mmio_read_16(addr) & mask; in polling_with_timeout()
136 data = mmio_read_32(addr) & mask; in polling_with_timeout()
137 } while (data != val && --usec_timeout > 0); in polling_with_timeout()
140 return data; in polling_with_timeout()
145 static inline void reg_set(uintptr_t addr, uint32_t data, uint32_t mask) in reg_set() argument
148 addr, data, mask); in reg_set()
150 mmio_clrsetbits_32(addr, mask, data & mask); in reg_set()
155 static inline void __unused reg_set16(uintptr_t addr, uint16_t data, in reg_set16() argument
160 addr, data, mask); in reg_set16()
[all …]
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| /rk3399_ARM-atf/plat/intel/soc/agilex5/soc/ |
| H A D | agilex5_memory_controller.c | 92 uint32_t data; in clear_emif() local
99 data = mmio_read_32(AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT); in clear_emif()
100 if ((data & AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE) == 0) in clear_emif()
113 uint32_t data; in mem_calibration() local
125 data = mmio_read_32(AGX_MPFE_HMC_ADP_DDRCALSTAT); in mem_calibration()
126 if (AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 1) in mem_calibration()
131 if (AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) { in mem_calibration()
140 if (AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) { in mem_calibration()
176 uint32_t data, dram_addr_order, ddr_conf, bank, row, col, in configure_ddr_sched_ctrl_regs() local
185 data = mmio_read_32(AGX_MPFE_IOHMC_CTRLCFG1); in configure_ddr_sched_ctrl_regs()
[all …]
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| /rk3399_ARM-atf/plat/intel/soc/agilex/soc/ |
| H A D | agilex_memory_controller.c | 91 uint32_t data; in clear_emif() local
98 data = mmio_read_32(AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT); in clear_emif()
99 if ((data & AGX_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE) == 0) in clear_emif()
112 uint32_t data; in mem_calibration() local
124 data = mmio_read_32(AGX_MPFE_HMC_ADP_DDRCALSTAT); in mem_calibration()
125 if (AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 1) in mem_calibration()
130 if (AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) { in mem_calibration()
139 if (AGX_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) { in mem_calibration()
175 uint32_t data, dram_addr_order, ddr_conf, bank, row, col, in configure_ddr_sched_ctrl_regs() local
184 data = mmio_read_32(AGX_MPFE_IOHMC_CTRLCFG1); in configure_ddr_sched_ctrl_regs()
[all …]
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| /rk3399_ARM-atf/plat/common/ |
| H A D | ubsan.c | 72 void __ubsan_handle_type_mismatch_abort(struct type_mismatch_data *data,
74 void __ubsan_handle_type_mismatch_v1_abort(struct type_mismatch_data *data,
76 void __ubsan_handle_add_overflow_abort(struct overflow_data *data,
78 void __ubsan_handle_sub_overflow_abort(struct overflow_data *data,
80 void __ubsan_handle_mul_overflow_abort(struct overflow_data *data,
82 void __ubsan_handle_negate_overflow_abort(struct overflow_data *data,
84 void __ubsan_handle_pointer_overflow_abort(struct overflow_data *data,
86 void __ubsan_handle_divrem_overflow_abort(struct overflow_data *data,
88 void __ubsan_handle_shift_out_of_bounds_abort(struct shift_out_of_bounds_data *data,
90 void __ubsan_handle_out_of_bounds_abort(struct out_of_bounds_data *data,
[all …]
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| /rk3399_ARM-atf/plat/intel/soc/stratix10/soc/ |
| H A D | s10_memory_controller.c | 95 uint32_t data; in clear_emif() local
102 data = mmio_read_32(S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT); in clear_emif()
103 if ((data & S10_MPFE_HMC_ADP_RSTHANDSHAKESTAT_SEQ2CORE) == 0) in clear_emif()
116 uint32_t data; in mem_calibration() local
128 data = mmio_read_32(S10_MPFE_HMC_ADP_DDRCALSTAT); in mem_calibration()
129 if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 1) in mem_calibration()
134 if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) { in mem_calibration()
143 if (S10_MPFE_HMC_ADP_DDRCALSTAT_CAL(data) == 0) { in mem_calibration()
204 uint32_t data, dram_addr_order, ddr_conf, bank, row, col, in configure_ddr_sched_ctrl_regs() local
213 data = mmio_read_32(S10_MPFE_IOHMC_CTRLCFG1); in configure_ddr_sched_ctrl_regs()
[all …]
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| /rk3399_ARM-atf/plat/brcm/board/common/ |
| H A D | platform_common.c | 16 uint32_t data; in boot_source_get() local
19 data = FORCE_BOOTSOURCE; in boot_source_get()
22 data = mmio_read_32(CRMU_IHOST_SW_PERSISTENT_REG1); in boot_source_get()
23 if (data & BOOT_SOURCE_SOFT_ENABLE_MASK) { in boot_source_get()
24 data >>= BOOT_SOURCE_SOFT_DATA_OFFSET; in boot_source_get()
33 data = 0; in boot_source_get()
35 data |= 0x1; in boot_source_get()
37 data |= 0x2; in boot_source_get()
39 data |= 0x4; in boot_source_get()
51 data = mmio_read_32(ROM_S0_IDM_IO_STATUS); in boot_source_get()
[all …]
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| /rk3399_ARM-atf/plat/imx/imx8m/ddr/ |
| H A D | ddr4_dvfs.c | 12 void ddr4_mr_write(uint32_t mr, uint32_t data, uint32_t mr_type, in ddr4_mr_write() argument
47 data_mirror = (data & 0x1607) | ((data & 0x8) << 1) | ((data & 0x10) >> 1) | in ddr4_mr_write()
48 ((data & 0x20) << 1) | ((data & 0x40) >> 1) | ((data & 0x80) << 1) | in ddr4_mr_write()
49 ((data & 0x100) >> 1) | ((data & 0x800) << 2) | ((data & 0x2000) >> 2) ; in ddr4_mr_write()
51 data_mirror = (data & 0xfe07) | ((data & 0x8) << 1) | ((data & 0x10) >> 1) | in ddr4_mr_write()
52 ((data & 0x20) << 1) | ((data & 0x40) >> 1) | ((data & 0x80) << 1) | in ddr4_mr_write()
53 ((data & 0x100) >> 1); in ddr4_mr_write()
57 data_mirror = data; in ddr4_mr_write()
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| /rk3399_ARM-atf/plat/hisilicon/hikey960/ |
| H A D | hikey960_bl1_setup.c | 111 unsigned int data, mask; in hikey960_ufs_reset() local
116 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); in hikey960_ufs_reset()
117 } while (data & BIT_SYSCTRL_REF_CLOCK_EN); in hikey960_ufs_reset()
128 data = mmio_read_32(CRG_PERRSTSTAT3_REG); in hikey960_ufs_reset()
129 } while ((data & PERI_UFS_BIT) == 0); in hikey960_ufs_reset()
140 data = SC_DIV_UFSPHY_CFG(3); in hikey960_ufs_reset()
141 mmio_write_32(CRG_CLKDIV16_REG, mask | data); in hikey960_ufs_reset()
142 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); in hikey960_ufs_reset()
143 data &= ~MASK_SYSCTRL_CFG_CLOCK_FREQ; in hikey960_ufs_reset()
144 data |= 0x39; in hikey960_ufs_reset()
[all …]
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| /rk3399_ARM-atf/plat/brcm/board/stingray/driver/ |
| H A D | swreg.c | 30 #define BSTI_CMD(sb, op, pa, ra, ta, data) \ argument
33 (((ta) & 0x3) << 16) | (data))
45 #define UPDATE_POS_EDGE(data, set) ((data) | ((set) << 1)) argument
144 uint32_t data; in swreg_poll() local
148 data = mmio_read_32(BSTI_CONTROL_OFFSET); in swreg_poll()
149 if ((data & BSTI_CONTROL_BUSY) != BSTI_CONTROL_BUSY) in swreg_poll()
158 static int write_swreg_config(enum sw_reg reg_id, uint32_t addr, uint32_t data) in write_swreg_config() argument
163 cmd = BSTI_CMD(0x1, BSTI_WRITE, reg_id, addr, BSTI_COMMAND_TA, data); in write_swreg_config()
175 static int read_swreg_config(enum sw_reg reg_id, uint32_t addr, uint32_t *data) in read_swreg_config() argument
190 *data = mmio_read_32(BSTI_COMMAND_OFFSET); in read_swreg_config()
[all …]
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| /rk3399_ARM-atf/drivers/renesas/rcar_gen4/mssr/ |
| H A D | mssr.c | 26 void rcar_mssr_clock(unsigned int n, uint32_t data, bool on, bool force) in rcar_mssr_clock() argument
33 next_status = prev_status & ~data; in rcar_mssr_clock()
35 next_status = prev_status | data; in rcar_mssr_clock()
43 while ((data & mmio_read_32(MSSR_MSTPSR(n))) != 0) in rcar_mssr_clock()
46 while ((data & mmio_read_32(MSSR_MSTPSR(n))) == 0) in rcar_mssr_clock()
50 void rcar_mssr_soft_reset(unsigned int n, uint32_t data, bool assert, bool force) in rcar_mssr_soft_reset() argument
57 next_status = prev_status | data; in rcar_mssr_soft_reset()
59 next_status = prev_status & ~data; in rcar_mssr_soft_reset()
65 cpg_write_32(MSSR_SRCR(n), data); in rcar_mssr_soft_reset()
67 cpg_write_32(MSSR_SRSTCLR(n), data); in rcar_mssr_soft_reset()
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| /rk3399_ARM-atf/plat/intel/soc/common/lib/utils/ |
| H A D | alignment_utils.c | 24 bool is_8_bytes_aligned(uint32_t data) in is_8_bytes_aligned() argument
26 if ((data % (MBOX_WORD_BYTE * 2U)) != 0U) { in is_8_bytes_aligned()
34 bool is_16_bytes_aligned(uint32_t data) in is_16_bytes_aligned() argument
36 if ((data % (MBOX_WORD_BYTE * 4U)) != 0U) in is_16_bytes_aligned()
42 bool is_32_bytes_aligned(uint32_t data) in is_32_bytes_aligned() argument
44 if ((data % (8U * MBOX_WORD_BYTE)) != 0U) { in is_32_bytes_aligned()
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| /rk3399_ARM-atf/drivers/auth/tbbr/ |
| H A D | tbbr_cot_bl2.c | 96 .data = &raw_data,
117 .data = &raw_data
131 .data = {
138 .data = {
159 .data = &raw_data
173 .data = {
191 .data = &raw_data
205 .data = {
220 .data = &raw_data,
240 .data = &raw_data
[all …]
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| /rk3399_ARM-atf/drivers/nxp/auth/tbbr/ |
| H A D | tbbr_cot.c | 146 .data = &raw_data
160 .data = {
167 .data = {
189 .data = &raw_data
203 .data = {
221 .data = &raw_data
235 .data = {
242 .data = {
257 .data = &raw_data,
272 .data = &raw_data,
[all …]
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| /rk3399_ARM-atf/plat/arm/board/juno/ |
| H A D | juno_tbbr_cot_bl2.c | 111 .data = &raw_data
125 .data = {
132 .data = {
153 .data = &raw_data
167 .data = {
185 .data = &raw_data
199 .data = {
214 .data = &raw_data,
234 .data = &raw_data
248 .data = {
[all …]
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| /rk3399_ARM-atf/plat/mediatek/mt8183/drivers/sspm/ |
| H A D | sspm.c | 31 int sspm_mbox_read(uint32_t slot, uint32_t *data, uint32_t len) in sspm_mbox_read() argument
38 if (data) in sspm_mbox_read()
39 memcpy_from_sspm(data, in sspm_mbox_read()
46 int sspm_mbox_write(uint32_t slot, uint32_t *data, uint32_t len) in sspm_mbox_write() argument
53 if (data) in sspm_mbox_write()
55 data, in sspm_mbox_write()
79 int sspm_ipi_send_non_blocking(uint32_t id, uint32_t *data) in sspm_ipi_send_non_blocking() argument
89 data, in sspm_ipi_send_non_blocking()
95 data, in sspm_ipi_send_non_blocking()
105 int sspm_ipi_recv_non_blocking(uint32_t id, uint32_t *data, uint32_t len) in sspm_ipi_recv_non_blocking() argument
[all …]
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| /rk3399_ARM-atf/drivers/marvell/mochi/ |
| H A D | cp110_setup.c | 155 uint32_t data; in cp110_errata_wa_init() local
167 data = mmio_read_32(base + MVEBU_SOC_CFG_REG(MVEBU_SOC_CFG_REG_NUM)); in cp110_errata_wa_init()
168 data &= ~MVEBU_SOC_CFG_GLOG_SECURE_EN_MASK; in cp110_errata_wa_init()
169 mmio_write_32(base + MVEBU_SOC_CFG_REG(MVEBU_SOC_CFG_REG_NUM), data); in cp110_errata_wa_init()
247 uint32_t index, data; in cp110_axi_attr_init() local
266 data = mmio_read_32(base + MVEBU_AXI_ATTR_REG(index)); in cp110_axi_attr_init()
267 data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK; in cp110_axi_attr_init()
268 data |= (CACHE_ATTR_WRITE_ALLOC | in cp110_axi_attr_init()
272 data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK; in cp110_axi_attr_init()
273 data |= (CACHE_ATTR_READ_ALLOC | in cp110_axi_attr_init()
[all …]
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| /rk3399_ARM-atf/tools/amlogic/ |
| H A D | doimage.c | 25 static inline int fdwrite(int fd, uint8_t *data, size_t len) in fdwrite() argument
32 nr = write(fd, data + l, len - l); in fdwrite()
48 uint32_t data; in main() local
68 data = htole32(BL31_MAGIC); in main()
69 if (fdwrite(fout, (uint8_t *)&data, sizeof(data)) < 0) in main()
73 data = htole32(BL31_LOADADDR); in main()
74 if (fdwrite(fout, (uint8_t *)&data, sizeof(data)) < 0) in main()
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| /rk3399_ARM-atf/drivers/synopsys/emmc/ |
| H A D | dw_mmc.c | 143 unsigned int data; in dw_update_clk() local
149 data = mmio_read_32(dw_params.reg_base + DWMMC_CMD); in dw_update_clk()
150 if ((data & CMD_START) == 0) in dw_update_clk()
152 data = mmio_read_32(dw_params.reg_base + DWMMC_RINTSTS); in dw_update_clk()
153 assert((data & INT_HLE) == 0); in dw_update_clk()
159 unsigned int data; in dw_set_clk() local
173 data = mmio_read_32(dw_params.reg_base + DWMMC_STATUS); in dw_set_clk()
174 } while (data & STATUS_DATA_BUSY); in dw_set_clk()
191 unsigned int data; in dw_init() local
200 data = mmio_read_32(base + DWMMC_CTRL); in dw_init()
[all …]
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| /rk3399_ARM-atf/drivers/auth/dualroot/ |
| H A D | bl1_cot.c | 64 .data = &raw_data
78 .data = {
85 .data = {
92 .data = {
108 .data = &raw_data,
124 .data = &raw_data,
139 .data = &raw_data,
158 .data = &raw_data
165 .data = {
172 .data = {
[all …]
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| /rk3399_ARM-atf/tools/cert_create/src/ |
| H A D | sha.c | 34 unsigned char data[BUFFER_SIZE]; in sha_file() local
77 while ((bytes = fread(data, 1, BUFFER_SIZE, inFile)) != 0) { in sha_file()
78 EVP_DigestUpdate(mdctx, data, bytes); in sha_file()
95 while ((bytes = fread(data, 1, BUFFER_SIZE, inFile)) != 0) { in sha_file()
96 SHA384_Update(&sha512Context, data, bytes); in sha_file()
101 while ((bytes = fread(data, 1, BUFFER_SIZE, inFile)) != 0) { in sha_file()
102 SHA512_Update(&sha512Context, data, bytes); in sha_file()
107 while ((bytes = fread(data, 1, BUFFER_SIZE, inFile)) != 0) { in sha_file()
108 SHA256_Update(&shaContext, data, bytes); in sha_file()
|