1 /*
2 * Copyright (c) 2015-2025, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <common/debug.h>
8 #include <lib/mmio.h>
9 #include <lib/utils_def.h>
10
11 #define CPG_BASE 0xE6150000U
12 #define CPG_CPGWPR (CPG_BASE + 0x000U)
13
14 #define MSSR_BASE CPG_BASE
15 #define MSSR_SRCR(n) (MSSR_BASE + 0x2C00U + (n) * 4)
16 #define MSSR_SRSTCLR(n) (MSSR_BASE + 0x2C80U + (n) * 4)
17 #define MSSR_MSTPCR(n) (MSSR_BASE + 0x2D00U + (n) * 4)
18 #define MSSR_MSTPSR(n) (MSSR_BASE + 0x2E00U + (n) * 4)
19
cpg_write_32(uint32_t addr,uint32_t val)20 static void cpg_write_32(uint32_t addr, uint32_t val)
21 {
22 mmio_write_32(CPG_CPGWPR, ~val);
23 mmio_write_32(addr, val);
24 }
25
rcar_mssr_clock(unsigned int n,uint32_t data,bool on,bool force)26 void rcar_mssr_clock(unsigned int n, uint32_t data, bool on, bool force)
27 {
28 uint32_t prev_status, next_status;
29
30 prev_status = mmio_read_32(MSSR_MSTPSR(n));
31
32 if (on)
33 next_status = prev_status & ~data;
34 else
35 next_status = prev_status | data;
36
37 if (!force && (prev_status == next_status))
38 return;
39
40 cpg_write_32(MSSR_MSTPCR(n), next_status);
41
42 if (on)
43 while ((data & mmio_read_32(MSSR_MSTPSR(n))) != 0)
44 ;
45 else
46 while ((data & mmio_read_32(MSSR_MSTPSR(n))) == 0)
47 ;
48 }
49
rcar_mssr_soft_reset(unsigned int n,uint32_t data,bool assert,bool force)50 void rcar_mssr_soft_reset(unsigned int n, uint32_t data, bool assert, bool force)
51 {
52 uint32_t prev_status, next_status;
53
54 prev_status = mmio_read_32(MSSR_SRCR(n));
55
56 if (assert)
57 next_status = prev_status | data;
58 else
59 next_status = prev_status & ~data;
60
61 if (!force && (prev_status == next_status))
62 return;
63
64 if (assert)
65 cpg_write_32(MSSR_SRCR(n), data);
66 else
67 cpg_write_32(MSSR_SRSTCLR(n), data);
68 }
69
rcar_mssr_setup(void)70 void rcar_mssr_setup(void)
71 {
72 /* INTC-AP de-assert */
73 rcar_mssr_soft_reset(5, BIT(31), 0, 0);
74 rcar_mssr_soft_reset(11, BIT(19), 0, 0);
75
76 /* INTC-AP clock on */
77 rcar_mssr_clock(5, BIT(31), 1, 0);
78 }
79