| /rk3399_ARM-atf/docs/plat/ |
| H A D | mt8189.rst | 5 The chip incorporates eight cores - six Cortex-A55 cores, two Cortex-A78
6 cores.
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| H A D | mt8196.rst | 5 The chip incorporates eight cores - four Cortex-A720 cores, three Cortex-X4
6 cores and one Cortex-X925 core.
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| H A D | mt8183.rst | 5 The chip incorporates eight cores - four Cortex-A53 little cores and Cortex-A73.
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| H A D | mt8186.rst | 5 The chip incorporates eight cores - six Cortex-A55 little cores and two Cortex-A76.
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| H A D | mt8192.rst | 5 The chip incorporates eight cores - four Cortex-A55 little cores and Cortex-A76.
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| H A D | mt8195.rst | 5 The chip incorporates eight cores - four Cortex-A55 little cores and Cortex-A78.
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| H A D | mt8188.rst | 5 The chip incorporates eight cores - six Cortex-A55 little cores and two Cortex-A78.
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| H A D | nvidia-tegra.rst | 7 T194 has eight NVIDIA Carmel CPU cores in a coherent multi-processor
8 configuration. The Carmel cores support the ARM Architecture version 8.2,
13 eight cores if required.
22 T186 has Dual NVIDIA Denver2 ARM® CPU cores, plus Quad ARM Cortex®-A57 cores,
23 in a coherent multiprocessor configuration. The Denver 2 and Cortex-A57 cores
30 heterogeneous multi-processing with all six cores if required.
33 fully Armv8-A architecture compatible. Each of the two Denver cores
37 cache, which services both cores.
60 T210 has Quad Arm® Cortex®-A57 cores in a switched configuration with a
61 companion set of quad Arm Cortex-A53 cores. The Cortex-A57 and A53 cores
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| H A D | ast2700.rst | 4 Aspeed AST2700 is a 64-bit ARM SoC with 4-cores Cortex-A35 integrated.
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| H A D | rpi3.rst | 5 Arm Cortex-A53 cores.
25 card) and is located between all Arm cores and the DRAM. Check the `Raspberry Pi
30 the cores boot in AArch64 mode.
40 the cores are powered on at the same time and start at address **0x0**.
48 Ideally, we want to load the kernel and have all cores available, which means
49 that we need to make the secondary cores work in the way the kernel expects, as
50 explained in `Secondary cores`_. In practice, a small bootstrap is needed
89 All addresses are Physical Addresses from the point of view of the Arm cores.
139 different mappings than the Arm cores in which the I/O addresses don't overlap
162 Secondary cores
[all …]
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| H A D | brcm-stingray.rst | 6 Broadcom's Stingray(BCM958742t) is a multi-core processor with 8 Cortex-A72 cores.
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| H A D | allwinner.rst | 5 SoCs with ARMv8 cores. Only BL31 is used to provide proper EL3 setup and
48 - ``SUNXI_PSCI_USE_NATIVE`` : Support direct control of the CPU cores powerdown
57 - ``SUNXI_PSCI_USE_SCPI`` : Support control of the CPU cores powerdown and
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| /rk3399_ARM-atf/docs/components/ |
| H A D | mpmm.rst | 5 some Arm Armv9-A cores, beginning with the Cortex-X2, Cortex-A710 and
6 Cortex-A510 cores. This mechanism detects and limits high-activity events to
17 limiting the number of cores that can execute higher-activity workloads or
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| /rk3399_ARM-atf/plat/qemu/qemu_sbsa/ |
| H A D | sbsa_sip_svc.c | 90 if (topology.cores > 0) { in sbsa_sip_smc_handler()
92 topology.clusters, topology.cores, in sbsa_sip_smc_handler()
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| H A D | sbsa_platform.c | 61 dynamic_platform_info.cpu_topo.cores = in read_cpu_topology_from_dt()
70 dynamic_platform_info.cpu_topo.cores, in read_cpu_topology_from_dt()
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| /rk3399_ARM-atf/fdts/ |
| H A D | arm_fpga.dts | 6 * Number and kind of CPU cores differs from image to image, so the
54 /* This node will be removed at runtime on cores without SPE. */
97 /* The GICR size will be adjusted at runtime to match the cores. */
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| /rk3399_ARM-atf/plat/qemu/qemu_sbsa/include/ |
| H A D | sbsa_platform.h | 34 uint32_t cores; member
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| /rk3399_ARM-atf/include/plat/arm/common/ |
| H A D | fconf_ethosn_getter.h | 50 struct ethosn_core_t cores[ETHOSN_DEV_CORE_NUM_MAX]; member
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| /rk3399_ARM-atf/docs/perf/ |
| H A D | psci-performance-n1sdp.rst | 175 .. table:: ``CPU_VERSION`` latency (ns) in parallel on all cores (v2.14)
189 .. table:: ``CPU_VERSION`` latency (ns) in parallel on all cores (v2.13)
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| /rk3399_ARM-atf/docs/plat/arm/fvp/ |
| H A D | fvp-build-options.rst | 46 inactive/fused CPU cores as read-only. The default value of this option
47 is ``0``, which means the redistributor pages of all CPU cores are marked
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| H A D | fvp-support.rst | 16 Arm FVPs without shifted affinities, and that do not support threaded CPU cores
55 CPU cores (64-bit host machine only).
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| /rk3399_ARM-atf/docs/plat/arm/arm_fpga/ |
| H A D | index.rst | 5 testing and bringup of new cores. With that focus, peripheral support is
22 As the number and topology layout of the CPU cores differs significantly
32 internal list, but for new or experimental cores this creates a lot of
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| /rk3399_ARM-atf/docs/plat/st/ |
| H A D | stm32mp2.rst | 54 - STM32MP257: Dual Cortex-A35 cores, Cortex-M33 core - 3x Ethernet (2+1 switch) - 3x CAN FD – H264 …
55 - STM32MP255: Dual Cortex-A35 cores, Cortex-M33 core - 2x Ethernet – 3x CAN FD - H264 - 3D GPU – AI…
56 - STM32MP253: Dual Cortex-A35 cores, Cortex-M33 core - 2x Ethernet – 3x CAN FD - LVDS
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| /rk3399_ARM-atf/docs/security_advisories/ |
| H A D | security-advisory-tfv-9.rst | 52 TF-A using the loop workaround(all cores that implement FEAT_CSV2 except the
91 For all other cores impacted by Spectre-BHB, some of which that do not implement
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| /rk3399_ARM-atf/docs/design_documents/ |
| H A D | psci_osi_mode.rst | 63 between cores.
160 :retval DENIED: if the cores are not in the correct state.
165 * All cores are in one of the following states:
171 * None of the cores has called CPU_SUSPEND since the last change of mode or
174 Switching from OS-initiated to platform-coordinated is only allowed if all cores
207 all cores to determine the deepest power state to enter.
278 cores in a topology node call CPU_OFF, the last core will power down the node.
280 In OS-initiated mode, if a subset of the cores in a topology node has called
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