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Searched refs:config (Results 1 – 25 of 186) sorted by relevance

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/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/src/
H A Dddrphy_phyinit_initstruct.c18 void ddrphy_phyinit_initstruct(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d) in ddrphy_phyinit_initstruct() argument
136 mb_ddr_1d->sequencectrl = (uint16_t)config->uia.sequencectrl; in ddrphy_phyinit_initstruct()
142 mb_ddr_1d->phyvref = (uint8_t)config->uia.phyvref; in ddrphy_phyinit_initstruct()
159 mb_ddr_1d->enableddqs = (uint8_t)((config->uib.numactivedbytedfi0 + in ddrphy_phyinit_initstruct()
160 config->uib.numactivedbytedfi1) * 8U); in ddrphy_phyinit_initstruct()
162 mb_ddr_1d->phycfg = (uint8_t)config->uia.is2ttiming; in ddrphy_phyinit_initstruct()
164 mb_ddr_1d->phycfg = ((config->uim.mr3 & 0x8U) == 0x8U) ? in ddrphy_phyinit_initstruct()
165 0U : (uint8_t)config->uia.is2ttiming; in ddrphy_phyinit_initstruct()
166 mb_ddr_1d->x16present = (config->uib.dramdatawidth == 0x10) ? in ddrphy_phyinit_initstruct()
177 mb_ddr_1d->mr0 = (uint16_t)config->uim.mr0; in ddrphy_phyinit_initstruct()
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H A Dddrphy_phyinit_isdbytedisabled.c18 int ddrphy_phyinit_isdbytedisabled(struct stm32mp_ddr_config *config, in ddrphy_phyinit_isdbytedisabled() argument
28 disabledbyte = (dbytenumber > (config->uib.numactivedbytedfi0 - 1U)) ? 1 : 0; in ddrphy_phyinit_isdbytedisabled()
30 nad0 = config->uib.numactivedbytedfi0; in ddrphy_phyinit_isdbytedisabled()
31 nad1 = config->uib.numactivedbytedfi1; in ddrphy_phyinit_isdbytedisabled()
33 if ((nad0 + nad1) > config->uib.numdbyte) { in ddrphy_phyinit_isdbytedisabled()
37 nad0, nad1, config->uib.numdbyte); in ddrphy_phyinit_isdbytedisabled()
40 if (config->uib.dfi1exists != 0U) { in ddrphy_phyinit_isdbytedisabled()
41 if (config->uib.numactivedbytedfi1 == 0U) { in ddrphy_phyinit_isdbytedisabled()
43 disabledbyte = (dbytenumber > (config->uib.numactivedbytedfi0 - 1U)) ? in ddrphy_phyinit_isdbytedisabled()
47 disabledbyte = (((config->uib.numactivedbytedfi0 - 1U) < dbytenumber) && in ddrphy_phyinit_isdbytedisabled()
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H A Dddrphy_phyinit_c_initphyconfig.c24 static void txslewrate_program(struct stm32mp_ddr_config *config) in txslewrate_program() argument
40 txprep = config->uia.txslewrisedq; in txslewrate_program()
41 txpren = config->uia.txslewfalldq; in txslewrate_program()
47 for (byte = 0U; byte < config->uib.numdbyte; byte++) { in txslewrate_program()
69 static void atxslewrate_program(struct stm32mp_ddr_config *config) in atxslewrate_program() argument
76 atxprep = config->uia.txslewriseac; in atxslewrate_program()
77 atxpren = config->uia.txslewfallac; in atxslewrate_program()
83 if (config->uib.numanib == 8U) { in atxslewrate_program()
88 for (anib = 0U; anib < config->uib.numanib; anib++) { in atxslewrate_program()
146 static void pllctrl2_program(struct stm32mp_ddr_config *config) in pllctrl2_program() argument
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H A Dddrphy_phyinit_sequence.c20 int ddrphy_phyinit_sequence(struct stm32mp_ddr_config *config, bool skip_training, bool reten) in ddrphy_phyinit_sequence() argument
32 if (config->uib.numpstates > 1U) { in ddrphy_phyinit_sequence()
37 ddrphy_phyinit_initstruct(config, &mb_ddr_1d); in ddrphy_phyinit_sequence()
40 ret = ddrphy_phyinit_calcmb(config, &mb_ddr_1d); in ddrphy_phyinit_sequence()
52 ret = ddrphy_phyinit_c_initphyconfig(config, &mb_ddr_1d, &ardptrinitval); in ddrphy_phyinit_sequence()
60 ddrphy_phyinit_usercustom_custompretrain(config); in ddrphy_phyinit_sequence()
70 ddrphy_phyinit_progcsrskiptrain(config, &mb_ddr_1d, ardptrinitval); in ddrphy_phyinit_sequence()
79 ret = ddrphy_phyinit_f_loaddmem(config, &mb_ddr_1d); in ddrphy_phyinit_sequence()
101 ddrphy_phyinit_i_loadpieimage(config, skip_training); in ddrphy_phyinit_sequence()
111 ret = ddrphy_phyinit_usercustom_saveretregs(config); in ddrphy_phyinit_sequence()
H A Dddrphy_phyinit_progcsrskiptrain.c40 static void dfimrl_program(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d, in dfimrl_program() argument
53 uifs = (1000 * 1000000) / ((int)config->uib.frequency * 2); in dfimrl_program()
72 for (byte = 0U; byte < config->uib.numdbyte; byte++) { in dfimrl_program()
104 static void txdqsdlytg_program(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d, argument
115 uifs = (1000 * 1000000) / ((int)config->uib.frequency * 2);
138 for (byte = 0U; byte < config->uib.numdbyte; byte++) {
146 if (ddrphy_phyinit_isdbytedisabled(config, mb_ddr_1d, byte) != 0) {
187 static void txdqdlytg_program(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d, argument
198 uifs = (1000 * 1000000) / ((int)config->uib.frequency * 2);
217 for (byte = 0U; byte < config->uib.numdbyte; byte++) {
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H A Dddrphy_phyinit_calcmb.c40 int ddrphy_phyinit_calcmb(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d) in ddrphy_phyinit_calcmb() argument
42 uint32_t nad0 = config->uib.numactivedbytedfi0; in ddrphy_phyinit_calcmb()
50 nad1 = config->uib.numactivedbytedfi1; in ddrphy_phyinit_calcmb()
54 if ((nad0 == 0U) || (config->uib.numdbyte == 0U)) { in ddrphy_phyinit_calcmb()
61 if ((nad0 + nad1) > config->uib.numdbyte) { in ddrphy_phyinit_calcmb()
68 if ((config->uib.dfi1exists == 0U) && (nad1 != 0U)) { in ddrphy_phyinit_calcmb()
90 if (config->uib.dimmtype == DDR_DIMMTYPE_NODIMM) { in ddrphy_phyinit_calcmb()
97 if (config->uib.dimmtype == DDR_DIMMTYPE_NODIMM) { in ddrphy_phyinit_calcmb()
112 ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_DRAMFREQ, config->uib.frequency * 2U); in ddrphy_phyinit_calcmb()
117 ret = ddrphy_phyinit_softsetmb(mb_ddr_1d, MB_FIELD_PLLBYPASSEN, config->uib.pllbypass); in ddrphy_phyinit_calcmb()
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H A Dddrphy_phyinit_i_loadpieimage.c49 static void seq0bdly_program(struct stm32mp_ddr_config *config) in seq0bdly_program() argument
61 dfifrq_x10 = (10U * (uint16_t)config->uib.frequency) / 2U; in seq0bdly_program()
66 if (config->uib.frequency < 400U) { in seq0bdly_program()
68 } else if (config->uib.frequency < 533U) { in seq0bdly_program()
109 static void seq0bdisableflag_program(struct stm32mp_ddr_config *config, bool skip_training) in seq0bdisableflag_program() argument
128 if (skip_training || (config->uia.disableretraining != 0U) || in seq0bdisableflag_program()
129 (config->uib.frequency < 333U)) { in seq0bdisableflag_program()
163 static void ppttrainsetup_program(struct stm32mp_ddr_config *config) in ppttrainsetup_program() argument
168 if (config->uib.frequency >= 333U) { in ppttrainsetup_program()
169 ppttrainsetup = (uint16_t)((config->uia.phymstrtraininterval << in ppttrainsetup_program()
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H A Dddrphy_phyinit_f_loaddmem.c28 int ddrphy_phyinit_f_loaddmem(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d) in ddrphy_phyinit_f_loaddmem() argument
36 if ((mb_ddr_1d->enableddqs > (8U * (uint8_t)config->uib.numactivedbytedfi0)) || in ddrphy_phyinit_f_loaddmem()
51 if ((mb_ddr_1d->enableddqscha > (uint8_t)(8U * config->uib.numactivedbytedfi0)) || in ddrphy_phyinit_f_loaddmem()
52 (mb_ddr_1d->enableddqschb > (uint8_t)(8U * config->uib.numactivedbytedfi1)) || in ddrphy_phyinit_f_loaddmem()
/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/mcsi/
H A Dmcsi.c80 unsigned int config = 0; in cci_enable_cluster_coherency() local
95 config |= SNOOP_EN_BIT; in cci_enable_cluster_coherency()
97 config |= DVM_EN_BIT; in cci_enable_cluster_coherency()
99 mmio_write_32(slave_base, support_ability | config); in cci_enable_cluster_coherency()
113 unsigned int config = 0; in cci_disable_cluster_coherency() local
121 config = mmio_read_32(slave_base); in cci_disable_cluster_coherency()
122 config &= ~(DVM_EN_BIT | SNOOP_EN_BIT); in cci_disable_cluster_coherency()
125 mmio_write_32(slave_base, config); in cci_disable_cluster_coherency()
138 unsigned int config; in cci_secure_switch() local
140 config = mmio_read_32(cci_base_addr + CENTRAL_CTRL_REG); in cci_secure_switch()
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/rk3399_ARM-atf/drivers/st/ddr/
H A Dstm32mp2_ram.c28 static int ddr_dt_get_ui_param(void *fdt, int node, struct stm32mp_ddr_config *config) in ddr_dt_get_ui_param() argument
34 ret = fdt_read_uint32_array(fdt, node, "st,phy-basic", size, (uint32_t *)&config->uib); in ddr_dt_get_ui_param()
43 ret = fdt_read_uint32_array(fdt, node, "st,phy-advanced", size, (uint32_t *)&config->uia); in ddr_dt_get_ui_param()
52 ret = fdt_read_uint32_array(fdt, node, "st,phy-mr", size, (uint32_t *)&config->uim); in ddr_dt_get_ui_param()
61 ret = fdt_read_uint32_array(fdt, node, "st,phy-swizzle", size, (uint32_t *)&config->uis); in ddr_dt_get_ui_param()
76 struct stm32mp_ddr_config config; in stm32mp2_ddr_setup() local
98 ret = stm32mp_ddr_dt_get_info(fdt, node, &config.info); in stm32mp2_ddr_setup()
103 ret = stm32mp_ddr_dt_get_param(fdt, node, param, ARRAY_SIZE(param), (uintptr_t)&config); in stm32mp2_ddr_setup()
108 ret = ddr_dt_get_ui_param(fdt, node, &config); in stm32mp2_ddr_setup()
113 config.self_refresh = false; in stm32mp2_ddr_setup()
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H A Dstm32mp2_ddr.c272 struct stm32mp_ddr_config *config) in ddr_sysconf_configuration() argument
278 (uint32_t)config->uib.pllbypass); in ddr_sysconf_configuration()
358 struct stm32mp_ddr_config *config) in stm32mp2_ddr_init() argument
364 if ((config->c_reg.mstr & DDRCTRL_MSTR_DDR3) != 0U) { in stm32mp2_ddr_init()
366 } else if ((config->c_reg.mstr & DDRCTRL_MSTR_DDR4) != 0U) { in stm32mp2_ddr_init()
368 } else if ((config->c_reg.mstr & DDRCTRL_MSTR_LPDDR4) != 0U) { in stm32mp2_ddr_init()
375 VERBOSE("name = %s\n", config->info.name); in stm32mp2_ddr_init()
376 VERBOSE("speed = %u kHz\n", config->info.speed); in stm32mp2_ddr_init()
377 VERBOSE("size = 0x%zx\n", config->info.size); in stm32mp2_ddr_init()
378 if (config->self_refresh) { in stm32mp2_ddr_init()
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H A Dstm32mp1_ram.c57 struct stm32mp_ddr_config config; in stm32mp1_ddr_setup() local
82 ret = stm32mp_ddr_dt_get_info(fdt, node, &config.info); in stm32mp1_ddr_setup()
87 ret = stm32mp_ddr_dt_get_param(fdt, node, param, ARRAY_SIZE(param), (uintptr_t)&config); in stm32mp1_ddr_setup()
95 stm32mp1_ddr_init(priv, &config); in stm32mp1_ddr_setup()
100 priv->info.size = config.info.size; in stm32mp1_ddr_setup()
116 uret = stm32mp_ddr_test_addr_bus(config.info.size); in stm32mp1_ddr_setup()
124 if (retsize < config.info.size) { in stm32mp1_ddr_setup()
126 retsize, config.info.size); in stm32mp1_ddr_setup()
/rk3399_ARM-atf/drivers/st/mce/
H A Dstm32_mce.c107 static int check_region_settings(struct stm32_mce_region_s *config) in check_region_settings() argument
111 if (config->encrypt_mode > MCE_ENCRYPTION_MODE_MAX) { in check_region_settings()
116 if ((config->start_address < STM32MP_DDR_BASE) || in check_region_settings()
117 (config->end_address < STM32MP_DDR_BASE)) { in check_region_settings()
123 if ((config->start_address > end) || (config->end_address > end)) { in check_region_settings()
128 if (config->start_address >= config->end_address) { in check_region_settings()
133 if (((config->start_address % MCE_ADDR_GRANULARITY) != 0U) || in check_region_settings()
134 (((config->end_address + 1U) % MCE_ADDR_GRANULARITY) != 0U)) { in check_region_settings()
148 static int stm32_mce_configure_region(uint32_t index, struct stm32_mce_region_s *config) in stm32_mce_configure_region() argument
152 if ((index >= MCE_IP_MAX_REGION_NB) || (config == NULL)) { in stm32_mce_configure_region()
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/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/include/
H A Dddrphy_phyinit_usercustom.h94 int ddrphy_phyinit_sequence(struct stm32mp_ddr_config *config, bool skip_training, bool reten);
96 int ddrphy_phyinit_c_initphyconfig(struct stm32mp_ddr_config *config,
99 void ddrphy_phyinit_progcsrskiptrain(struct stm32mp_ddr_config *config,
101 int ddrphy_phyinit_f_loaddmem(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d);
103 void ddrphy_phyinit_i_loadpieimage(struct stm32mp_ddr_config *config, bool skip_training);
106 int ddrphy_phyinit_calcmb(struct stm32mp_ddr_config *config, struct pmu_smb_ddr_1d *mb_ddr_1d);
109 int ddrphy_phyinit_isdbytedisabled(struct stm32mp_ddr_config *config,
114 void ddrphy_phyinit_usercustom_custompretrain(struct stm32mp_ddr_config *config);
116 int ddrphy_phyinit_usercustom_saveretregs(struct stm32mp_ddr_config *config);
/rk3399_ARM-atf/drivers/arm/gicv5/
H A Dgicv5_main.c66 static void iwb_enable(const struct gicv5_iwb *config) in iwb_enable() argument
68 uintptr_t base_addr = config->config_frame; in iwb_enable()
87 for (uint32_t i = 0U; i < config->num_wires; i++) { in iwb_enable()
88 assert(iwb_domain_supported(idr0, config->wires[i].domain)); in iwb_enable()
89 assert(config->wires[i].id <= num_regs * 32); in iwb_enable()
91 iwb_configure_domainr(base_addr, config->wires[i]); in iwb_enable()
92 iwb_configure_wtmr(base_addr, config->wires[i]); in iwb_enable()
110 static void irs_enable(const struct gicv5_irs *config) in irs_enable() argument
113 uintptr_t base_addr = config->el3_config_frame; in irs_enable()
121 assert(config->num_spis == 0U); in irs_enable()
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/rk3399_ARM-atf/lib/romlib/
H A Dromlib_generator.py93 self.config = None
97 self.config = self.args.parse_args(argv)
140 index_file_parser.parse(self.config.file)
142 with open(self.config.output, "w") as output_file:
151 if self.config.deps:
152 with open(self.config.deps, "w") as deps_file:
153 deps = [self.config.file] + index_file_parser.get_dependencies(self.config.file)
154 deps_file.write(self.config.output + ": " + " \\\n".join(deps) + "\n")
175 index_file_parser.parse(self.config.file)
177 with open(self.config.output, "w") as output_file:
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/rk3399_ARM-atf/tools/conventional-changelog-tf-a/
H A Dindex.js50 function writerOpts(config) { argument
64 const flattenedSections = flattenSections(config.sections);
93 sections: generateTemplateData(config.sections, noteGroup.notes),
127 sections: generateTemplateData(config.sections, commitGroup.commits),
134 const writerOpts = ccWriterOpts(config)
143 Handlebars.registerPartial("commitUrl", config.commitUrlFormat);
144 Handlebars.registerPartial("compareUrl", config.compareUrlFormat);
145 Handlebars.registerPartial("issueUrl", config.issueUrlFormat);
203 const config = parameter || {};
206 ccConventionalChangelog(config),
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/rk3399_ARM-atf/drivers/st/ddr/phy/phyinit/usercustom/
H A Dddrphy_phyinit_usercustom_custompretrain.c45 void ddrphy_phyinit_usercustom_custompretrain(struct stm32mp_ddr_config *config) in ddrphy_phyinit_usercustom_custompretrain() argument
57 (uint16_t)config->uis.swizzle[i]); in ddrphy_phyinit_usercustom_custompretrain()
63 mmio_write_32(base + (j * sizeof(uint32_t)), config->uis.swizzle[i]); in ddrphy_phyinit_usercustom_custompretrain()
66 for (byte = 0U; byte < config->uib.numdbyte; byte++) { in ddrphy_phyinit_usercustom_custompretrain()
72 (uint16_t)config->uis.swizzle[i]); in ddrphy_phyinit_usercustom_custompretrain()
80 (uint16_t)config->uis.swizzle[i]); in ddrphy_phyinit_usercustom_custompretrain()
87 (uint16_t)config->uis.swizzle[i]); in ddrphy_phyinit_usercustom_custompretrain()
/rk3399_ARM-atf/plat/arm/board/fvp/include/
H A Dfconf_hw_config_getter.h56 int fconf_populate_gicv3_config(uintptr_t config);
57 int fconf_populate_topology(uintptr_t config);
58 int fconf_populate_uart_config(uintptr_t config);
59 int fconf_populate_cpu_timer(uintptr_t config);
60 int fconf_populate_dram_layout(uintptr_t config);
61 int fconf_populate_pci_props(uintptr_t config);
/rk3399_ARM-atf/drivers/gpio/
H A Dgpio_spi.c16 static struct gpio_spi_config config; variable
25 return 500000 / config.spi_max_clock; in gpio_spi_get_delay_us()
30 return gpio_get_value(config.miso_gpio); in gpio_spi_miso()
35 gpio_set_value(config.sclk_gpio, bit); in gpio_spi_sclk()
40 gpio_set_value(config.mosi_gpio, bit); in gpio_spi_mosi()
45 gpio_set_value(config.cs_gpio, bit); in gpio_spi_cs()
109 switch (config.spi_mode) { in gpio_spi_xfer()
140 config = *gpio_spi_data; in gpio_spi_init()
/rk3399_ARM-atf/plat/arm/board/fvp/fdts/
H A Dfvp_fw_config.dts20 tb_fw-config {
26 hw-config {
36 * overlap BL2, BL31 or BL32. The NT firmware config
39 soc_fw-config {
45 /* If required, SPD should enable loading of trusted OS fw config */
47 tos_fw-config {
56 nt_fw-config {
/rk3399_ARM-atf/lib/fconf/
H A Dfconf.c46 void fconf_populate(const char *config_type, uintptr_t config) in fconf_populate() argument
48 assert(config != 0UL); in fconf_populate()
51 if (fdt_check_header((void *)config) != 0) { in fconf_populate()
56 INFO("FCONF: Reading %s firmware configuration file from: 0x%lx\n", config_type, config); in fconf_populate()
68 if (populator->populate(config) != 0) { in fconf_populate()
/rk3399_ARM-atf/include/lib/fconf/
H A Dfconf.h22 #define FCONF_REGISTER_POPULATOR(config, name, callback) \ argument
25 .config_type = (#config), \
44 int (*populate)(uintptr_t config);
57 void fconf_populate(const char *config_type, uintptr_t config);
/rk3399_ARM-atf/plat/arm/board/tc/fdts/
H A Dtc_fw_config.dts16 tb_fw-config {
22 tos_fw-config {
28 hw-config {
33 nt_fw-config {
/rk3399_ARM-atf/plat/intel/soc/common/include/
H A Dsocfpga_dt.h20 #define SOCFPGA_REGISTER_POPULATOR(config, name, callback) \ argument
23 .config_type = (#config), \
42 int (*populate)(uintptr_t config);

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