272 				      struct stm32mp_ddr_config *config)  in ddr_sysconf_configuration()  argument
278 		      (uint32_t)config->uib.pllbypass);  in ddr_sysconf_configuration()
358 		       struct stm32mp_ddr_config *config)  in stm32mp2_ddr_init()  argument
364 	if ((config->c_reg.mstr & DDRCTRL_MSTR_DDR3) != 0U) {  in stm32mp2_ddr_init()
366 	} else if ((config->c_reg.mstr & DDRCTRL_MSTR_DDR4) != 0U) {  in stm32mp2_ddr_init()
368 	} else if ((config->c_reg.mstr & DDRCTRL_MSTR_LPDDR4) != 0U) {  in stm32mp2_ddr_init()
375 	VERBOSE("name = %s\n", config->info.name);  in stm32mp2_ddr_init()
376 	VERBOSE("speed = %u kHz\n", config->info.speed);  in stm32mp2_ddr_init()
377 	VERBOSE("size  = 0x%zx\n", config->info.size);  in stm32mp2_ddr_init()
378 	if (config->self_refresh) {  in stm32mp2_ddr_init()
379 		VERBOSE("sel-refresh exit (zdata = 0x%x)\n", config->zdata);  in stm32mp2_ddr_init()
384 	if (config->self_refresh) {  in stm32mp2_ddr_init()
387 			config->self_refresh = false;  in stm32mp2_ddr_init()
391 	if (config->self_refresh) {  in stm32mp2_ddr_init()
414 		ddr_sysconf_configuration(priv, config);  in stm32mp2_ddr_init()
422 	config->c_reg.pwrctl |= DDRCTRL_PWRCTL_SELFREF_SW;  in stm32mp2_ddr_init()
425 	stm32mp_ddr_set_reg(priv, REG_REG, &config->c_reg, ddr_registers);  in stm32mp2_ddr_init()
426 	stm32mp_ddr_set_reg(priv, REG_TIMING, &config->c_timing, ddr_registers);  in stm32mp2_ddr_init()
427 	stm32mp_ddr_set_reg(priv, REG_MAP, &config->c_map, ddr_registers);  in stm32mp2_ddr_init()
428 	stm32mp_ddr_set_reg(priv, REG_PERF, &config->c_perf, ddr_registers);  in stm32mp2_ddr_init()
430 	if (!config->self_refresh) {  in stm32mp2_ddr_init()
437 	if (config->self_refresh) {  in stm32mp2_ddr_init()
441 		ret = ddrphy_phyinit_sequence(config, true, false);  in stm32mp2_ddr_init()
451 		ret = ddrphy_phyinit_sequence(config, false, true);  in stm32mp2_ddr_init()
461 	if (config->self_refresh) {  in stm32mp2_ddr_init()
475 		restore_refresh(priv->ctl, config->c_reg.rfshctl3, config->c_reg.pwrctl);  in stm32mp2_ddr_init()