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Searched refs:arg0 (Results 1 – 25 of 164) sorted by relevance

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/rk3399_ARM-atf/plat/imx/common/
H A Dimx_common.c22 int imx_bl31_params_parse(uintptr_t arg0, uintptr_t ocram_base, in imx_bl31_params_parse() argument
27 bl_params_t *v2 = (void *)(uintptr_t)arg0; in imx_bl31_params_parse()
29 if (arg0 & 0x3) { in imx_bl31_params_parse()
33 if (arg0 < ocram_base || arg0 >= ocram_base + ocram_size) { in imx_bl31_params_parse()
45 bl31_params_parse_helper(arg0, bl32_info, bl33_info); in imx_bl31_params_parse()
/rk3399_ARM-atf/plat/xilinx/common/include/
H A Dpm_api_sys.h57 #define PM_PACK_PAYLOAD1(pl, mid, flag, arg0) { \ argument
58 pl[0] = (uint32_t)(((uint32_t)(arg0) & 0xFFU) | \
62 #define PM_PACK_PAYLOAD2(pl, mid, flag, arg0, arg1) { \ argument
64 PM_PACK_PAYLOAD1(pl, (mid), (flag), (arg0)); \
67 #define PM_PACK_PAYLOAD3(pl, mid, flag, arg0, arg1, arg2) { \ argument
69 PM_PACK_PAYLOAD2(pl, (mid), (flag), (arg0), (arg1)); \
72 #define PM_PACK_PAYLOAD4(pl, mid, flag, arg0, arg1, arg2, arg3) { \ argument
74 PM_PACK_PAYLOAD3(pl, (mid), (flag), (arg0), (arg1), (arg2)); \
77 #define PM_PACK_PAYLOAD5(pl, mid, flag, arg0, arg1, arg2, arg3, arg4) { \ argument
79 PM_PACK_PAYLOAD4(pl, (mid), (flag), (arg0), (arg1), (arg2), (arg3)); \
[all …]
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/mce/
H A Dmce.c158 int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1, in mce_command_handler() argument
177 ret = ops->enter_cstate(cpu_ari_base, arg0, arg1); in mce_command_handler()
190 ret = ops->update_cstate_info(cpu_ari_base, (uint32_t)arg0, in mce_command_handler()
201 ret = ops->update_crossover_time(cpu_ari_base, arg0, arg1); in mce_command_handler()
206 ret64 = ops->read_cstate_stats(cpu_ari_base, arg0); in mce_command_handler()
215 ret = ops->write_cstate_stats(cpu_ari_base, arg0, arg1); in mce_command_handler()
220 ret = ops->is_ccx_allowed(cpu_ari_base, arg0, arg1); in mce_command_handler()
228 ret = ops->is_sc7_allowed(cpu_ari_base, arg0, arg1); in mce_command_handler()
237 ret = ops->online_core(cpu_ari_base, arg0); in mce_command_handler()
242 ret = ops->cc3_ctrl(cpu_ari_base, arg0, arg1, arg2); in mce_command_handler()
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/rk3399_ARM-atf/bl32/tsp/
H A Dtsp_common.c34 smc_args_t *set_smc_args(uint64_t arg0, in set_smc_args() argument
52 write_sp_arg(pcpu_smc_args, SMC_ARG0, arg0); in set_smc_args()
67 void tsp_setup(u_register_t arg0, u_register_t arg1, u_register_t arg2, in tsp_setup() argument
74 tsp_early_platform_setup(arg0, arg1, arg2, arg3); in tsp_setup()
84 smc_args_t *tsp_system_off_main(uint64_t arg0, in tsp_system_off_main() argument
112 smc_args_t *tsp_system_reset_main(uint64_t arg0, in tsp_system_reset_main() argument
H A Dtsp_private.h51 smc_args_t *set_smc_args(uint64_t arg0,
67 smc_args_t *tsp_cpu_suspend_main(uint64_t arg0,
76 smc_args_t *tsp_cpu_off_main(uint64_t arg0,
124 smc_args_t *tsp_system_reset_main(uint64_t arg0,
133 smc_args_t *tsp_system_off_main(uint64_t arg0,
/rk3399_ARM-atf/plat/xilinx/zynqmp/pm_service/
H A Dzynqmp_pm_api_sys.h41 #define PM_PACK_PAYLOAD1(pl, flag, arg0) { \ argument
42 pl[0] = ((uint32_t)(arg0) | ((uint32_t)(flag) << 24U)); \
45 #define PM_PACK_PAYLOAD2(pl, flag, arg0, arg1) { \ argument
47 PM_PACK_PAYLOAD1(pl, (flag), (arg0)); \
50 #define PM_PACK_PAYLOAD3(pl, flag, arg0, arg1, arg2) { \ argument
52 PM_PACK_PAYLOAD2(pl, (flag), (arg0), (arg1)); \
55 #define PM_PACK_PAYLOAD4(pl, flag, arg0, arg1, arg2, arg3) { \ argument
57 PM_PACK_PAYLOAD3(pl, (flag), (arg0), (arg1), (arg2)); \
60 #define PM_PACK_PAYLOAD5(pl, flag, arg0, arg1, arg2, arg3, arg4) { \ argument
62 PM_PACK_PAYLOAD4(pl, (flag), (arg0), (arg1), (arg2), (arg3)); \
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3399/
H A Dplat_sip_calls.c30 uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, in ddr_smc_handler() argument
35 return ddr_set_rate((uint32_t)arg0); in ddr_smc_handler()
37 return ddr_round_rate((uint32_t)arg0); in ddr_smc_handler()
41 dram_set_odt_pd(arg0, arg1, arg2); in ddr_smc_handler()
/rk3399_ARM-atf/plat/arm/common/sp_min/
H A Darm_sp_min_setup.c86 void arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in arm_sp_min_early_platform_setup() argument
124 bl33_image_ep_info.args.arg0 = 0U; in arm_sp_min_early_platform_setup()
134 bl_params_t *params_from_bl2 = (bl_params_t *)arg0; in arm_sp_min_early_platform_setup()
164 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
167 arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in plat_arm_sp_min_early_platform_setup()
188 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, in sp_min_early_platform_setup2() argument
191 plat_arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in sp_min_early_platform_setup2()
/rk3399_ARM-atf/plat/arm/board/fvp_ve/sp_min/
H A Dfvp_ve_sp_min_setup.c11 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
14 arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in plat_arm_sp_min_early_platform_setup()
/rk3399_ARM-atf/plat/arm/board/corstone700/sp_min/
H A Dcorstone700_sp_min_setup.c9 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
12 arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in plat_arm_sp_min_early_platform_setup()
/rk3399_ARM-atf/plat/arm/board/fvp/tsp/
H A Dfvp_tsp_setup.c11 void tsp_early_platform_setup(u_register_t arg0, u_register_t arg1, in tsp_early_platform_setup() argument
14 arm_tsp_early_platform_setup(arg0, arg1, arg2, arg3); in tsp_early_platform_setup()
/rk3399_ARM-atf/plat/arm/board/a5ds/sp_min/
H A Da5ds_sp_min_setup.c11 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, in plat_arm_sp_min_early_platform_setup() argument
14 arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); in plat_arm_sp_min_early_platform_setup()
/rk3399_ARM-atf/plat/nuvoton/npcm845x/
H A Dnpcm845x_bl31_setup.c134 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl31_early_platform_setup2() argument
137 arg0 = arg1 = arg2 = arg3 = 0; in bl31_early_platform_setup2()
139 void *from_bl2 = (void *)arg0; in bl31_early_platform_setup2()
180 bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE + in bl31_early_platform_setup2()
208 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE; in bl31_early_platform_setup2()
218 bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE; in bl31_early_platform_setup2()
/rk3399_ARM-atf/plat/arm/board/a5ds/
H A Da5ds_bl2_setup.c9 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl2_early_platform_setup2() argument
12 arm_bl2_early_platform_setup(arg0, arg1, arg2, arg3); in bl2_early_platform_setup2()
/rk3399_ARM-atf/bl2/
H A Dbl2_main.c42 void __no_pauth bl2_main(u_register_t arg0, u_register_t arg1, u_register_t arg2, in bl2_main() argument
52 bl2_el3_early_platform_setup(arg0, arg1, arg2, arg3); in bl2_main()
58 bl2_early_platform_setup2(arg0, arg1, arg2, arg3); in bl2_main()
/rk3399_ARM-atf/plat/arm/board/fvp_ve/
H A Dfvp_ve_bl2_setup.c16 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_… in bl2_early_platform_setup2() argument
18 arm_bl2_early_platform_setup(arg0, arg1, arg2, arg3); in bl2_early_platform_setup2()
/rk3399_ARM-atf/plat/rpi/rpi3/
H A Drpi3_bl31_setup.c70 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl31_early_platform_setup2() argument
84 bl_params_t *params_from_bl2 = (bl_params_t *) arg0; in bl31_early_platform_setup2()
122 bl33_image_ep_info.args.arg0 = 0U; in bl31_early_platform_setup2()
133 bl33_image_ep_info.args.arg0 = (u_register_t) RPI3_PRELOADED_DTB_BASE; in bl31_early_platform_setup2()
/rk3399_ARM-atf/plat/st/stm32mp2/
H A Dbl31_plat_setup.c21 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl31_early_platform_setup2() argument
80 assert(arg0 != 0UL); in bl31_early_platform_setup2()
81 params_from_bl2 = (bl_params_t *)arg0; in bl31_early_platform_setup2()
100 bl33_image_ep_info.args.arg0 = 0U; in bl31_early_platform_setup2()
/rk3399_ARM-atf/plat/brcm/common/
H A Dbrcm_bl31_setup.c133 bl33_image_ep_info.args.arg0 = (u_register_t)PRELOADED_DTB_BASE; in brcm_bl31_early_platform_setup()
181 bl33_image_ep_info.args.arg0 = (u_register_t)BL33_SHARED_DDR_BASE; in brcm_bl31_early_platform_setup()
188 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl31_early_platform_setup2() argument
195 brcm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); in bl31_early_platform_setup2()
197 plat_bcm_bl31_early_platform_setup((void *)arg0, (void *)arg3); in bl31_early_platform_setup2()
/rk3399_ARM-atf/plat/arm/common/
H A Darm_bl31_setup.c177 void __init arm_bl31_early_platform_setup(u_register_t arg0, u_register_t arg1, in arm_bl31_early_platform_setup() argument
193 bl33_image_ep_info.args.arg0 = PLAT_ARM_TRANSFER_LIST_DTB_OFFSET; in arm_bl31_early_platform_setup()
234 (void)arg0; in arm_bl31_early_platform_setup()
250 bl32_image_ep_info.args.arg0 = ARM_SPMC_MANIFEST_BASE; in arm_bl31_early_platform_setup()
288 bl_params_t *params_from_bl2 = (bl_params_t *)(uintptr_t)arg0; in arm_bl31_early_platform_setup()
348 if (bl33_image_ep_info.args.arg0 == 0U) { in arm_bl31_early_platform_setup()
349 bl33_image_ep_info.args.arg0 = HW_CONFIG_BASE; in arm_bl31_early_platform_setup()
361 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl31_early_platform_setup2() argument
367 arm_bl31_early_platform_setup(arg0, arg1, arg2, arg3); in bl31_early_platform_setup2()
/rk3399_ARM-atf/plat/mediatek/drivers/dfd/
H A Ddfd.c13 static u_register_t dfd_smc_dispatcher(u_register_t arg0, u_register_t arg1, in dfd_smc_dispatcher() argument
19 switch (arg0) { in dfd_smc_dispatcher()
/rk3399_ARM-atf/plat/arm/common/tsp/
H A Darm_tsp_setup.c45 void arm_tsp_early_platform_setup(u_register_t arg0, u_register_t arg1, in arm_tsp_early_platform_setup() argument
75 void tsp_early_platform_setup(u_register_t arg0, u_register_t arg1, in tsp_early_platform_setup() argument
78 arm_tsp_early_platform_setup(arg0, arg1, arg2, arg3); in tsp_early_platform_setup()
/rk3399_ARM-atf/lib/optee/
H A Doptee_utils.c146 header_ep->args.arg0 = MODE_RW_64; in parse_optee_header()
148 header_ep->args.arg0 = MODE_RW_32; in parse_optee_header()
200 header_ep->args.arg0 = MODE_RW_32; in parse_optee_header()
203 header_ep->args.arg0 = MODE_RW_64; in parse_optee_header()
/rk3399_ARM-atf/plat/imx/imx8m/imx8mn/
H A Dimx8mn_bl31_setup.c106 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl31_early_platform_setup2() argument
172 bl32_image_ep_info.args.arg0 = BL32_SIZE; in bl31_early_platform_setup2()
182 ret = imx_bl31_params_parse(arg0, IMX_NS_OCRAM_SIZE, IMX_NS_OCRAM_BASE, in bl31_early_platform_setup2()
185 imx_bl31_params_parse(arg0, IMX_TCM_BASE, IMX_TCM_SIZE, in bl31_early_platform_setup2()
257 args->arg0 = BL32_SIZE; in plat_trusty_set_boot_args()
/rk3399_ARM-atf/plat/arm/css/common/
H A Dcss_bl2_setup.c56 void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, in bl2_early_platform_setup2() argument
59 arm_bl2_early_platform_setup(arg0, arg1, arg2, arg3); in bl2_early_platform_setup2()

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