| /rk3399_ARM-atf/include/lib/cpus/aarch64/ |
| H A D | cpu_macros.S | 206 .macro add_erratum_entry _cpu:req, _cve:req, _id:req, _chosen:req, _split_wa=0
214 .quad check_erratum_\_cpu\()_\_id
216 .word \_id
255 .macro workaround_reset_start _cpu:req, _cve:req, _id:req, \
258 add_erratum_entry \_cpu, \_cve, \_id, \_chosen, \_split_wa
266 .pushsection .text.asm.erratum_\_cpu\()_\_id\()_wa, "ax"
270 bl check_erratum_\_cpu\()_\_id
273 cbz x0, erratum_\_cpu\()_\_id\()_skip_reset
283 .macro workaround_runtime_start _cpu:req, _cve:req, _id:req, _chosen:req, _midr
284 add_erratum_entry \_cpu, \_cve, \_id, \_chosen
[all …]
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| /rk3399_ARM-atf/plat/st/common/ |
| H A D | stm32mp_common.c | 39 #define BOARD_ID2NB(_id) (((_id) & BOARD_ID_BOARD_NB_MASK) >> \ argument
41 #define BOARD_ID2VARCPN(_id) (((_id) & BOARD_ID_VARCPN_MASK) >> \ argument
43 #define BOARD_ID2REV(_id) (((_id) & BOARD_ID_REVISION_MASK) >> \ argument
45 #define BOARD_ID2VARFG(_id) (((_id) & BOARD_ID_VARFG_MASK) >> \ argument
47 #define BOARD_ID2BOM(_id) ((_id) & BOARD_ID_BOM_MASK) argument
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| /rk3399_ARM-atf/include/lib/cpus/aarch32/ |
| H A D | cpu_macros.S | 168 .macro add_erratum_entry _cpu:req, _cve:req, _id:req, _chosen:req, _special
178 .word check_errata_cve_\_cve\()_\_id
180 .word check_errata_\_id
183 .word \_id
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| /rk3399_ARM-atf/plat/mediatek/drivers/gpio/ |
| H A D | mtgpio_common.h | 91 #define PIN(_id, _flag, _bit, _base, _offset) { \ argument
92 .id = _id, \
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| /rk3399_ARM-atf/plat/rockchip/rk3588/drivers/scmi/ |
| H A D | rk3588_rstd.c | 22 #define RK3588_SCMI_RESET(_id, _name, _attribute, _ops) \ argument
24 .id = _id, \
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| H A D | rk3588_clk.c | 177 #define RK3588_SCMI_CLOCK(_id, _name, _data, _table, _cnt, _is_s) \ argument
179 .id = _id, \
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| /rk3399_ARM-atf/plat/mediatek/mt8186/include/ |
| H A D | plat_pm.h | 47 #define IS_SPM_LP_SMC(_type, _id) (_id == (SPM_LP_SMC_MAGIC | _type)) argument
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| /rk3399_ARM-atf/plat/st/stm32mp1/ |
| H A D | stm32mp1_scmi.c | 73 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ argument
75 .clock_id = _id, \
110 #define RESET_CELL(_scmi_id, _id, _name) \ argument
112 .reset_id = _id, \
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| /rk3399_ARM-atf/plat/amd/versal2/ |
| H A D | scmi.c | 30 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled, _rate) \ argument
32 .clock_id = (_id), \
141 #define RESET_CELL(_scmi_id, _id, _name) \ argument
143 .reset_id = (_id), \
198 #define PD_CELL(_scmi_id, _id, _name, _state) \ argument
200 .pd_id = _id, \
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| /rk3399_ARM-atf/include/drivers/arm/ |
| H A D | gicv5.h | 167 #define WIRE_PROP_DESC(_id, _domain, _tm) \ argument
169 .id = (_id), \
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| /rk3399_ARM-atf/plat/mediatek/lib/pm/armv8_2/ |
| H A D | pwr_ctrl.c | 449 #define CPM_PM_FN_CHECK(_fns, _ops, _id, _func, _result, _flag) ({ \ argument
450 if ((_fns & _id)) { \
452 _flag |= _id; \
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| /rk3399_ARM-atf/plat/mediatek/lib/pm/armv9_0/ |
| H A D | pwr_ctrl.c | 424 #define CPM_PM_FN_CHECK(_fns, _ops, _id, _func, _cond_ex, _result, _flag) ({ \ argument
425 if ((_fns & _id)) { \
427 _flag |= _id; \
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| /rk3399_ARM-atf/drivers/st/clk/ |
| H A D | clk-stm32-core.h | 339 #define OSCILLATOR(idx_osc, _id, _name, _gate_id, _gate_rdy_id, _bypass, _css, _drive) \ argument
342 .id_clk = (_id),\
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| H A D | stm32mp1_clk.c | 123 #define DIV_CFG(_id, _offset, _shift, _width, _bitrdy)\ argument
124 [(_id)] = {\
153 #define MUXRDY_CFG(_id, _offset, _shift, _width, _bitrdy)\ argument
154 [(_id)] = {\
161 #define MUX_CFG(_id, _offset, _shift, _width)\ argument
162 MUXRDY_CFG(_id, _offset, _shift, _width, MUX_NO_BIT_RDY)
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| H A D | clk-stm32mp2.c | 1072 #define FLEXGEN(idx, _idx, _flags, _id)[idx] = {\ argument
1077 .id = _id,\
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| /rk3399_ARM-atf/plat/rockchip/rk3576/scmi/ |
| H A D | rk3576_clk.c | 232 #define RK3576_SCMI_CLOCK(_id, _name, _data, _table, _cnt, _is_s) \ argument
234 .id = _id, \
242 #define RK3576_SCMI_CLOCK_COM(_id, _name, _parent_table, _info, _data, \ argument
245 .id = _id, \
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| /rk3399_ARM-atf/docs/plat/ |
| H A D | nvidia-tegra.rst | 131 int uart\_id;
|