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Searched refs:PMU_BASE (Results 1 – 25 of 30) sorted by relevance

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/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/pmu/
H A Dpmu.c69 mmio_write_32(PMU_BASE + PMU_WAKEUP_INT_CON, WRITE_MASK_SET(BIT(WAKEUP_GPIO0_INT_EN))); in pmu_wakeup_source_config()
72 mmio_read_32(PMU_BASE + PMU_WAKEUP_INT_CON), PMU_WAKEUP_INT_CON); in pmu_wakeup_source_config()
88 mmio_write_32(PMU_BASE + PMU_PLLPD_CON, WRITE_MASK_SET(pll_id)); in pmu_pll_powerdown_config()
90 PMU_PLLPD_CON, mmio_read_32(PMU_BASE + PMU_PLLPD_CON)); in pmu_pll_powerdown_config()
95 mmio_write_32(PMU_BASE + PMU_DSU_STABLE_CNT, 0x180); in pmu_stable_count_config()
96 mmio_write_32(PMU_BASE + PMU_PMIC_STABLE_CNT, 0x180); in pmu_stable_count_config()
97 mmio_write_32(PMU_BASE + PMU_OSC_STABLE_CNT, 0x180); in pmu_stable_count_config()
98 mmio_write_32(PMU_BASE + PMU_WAKEUP_RSTCLR_CNT, 0x180); in pmu_stable_count_config()
99 mmio_write_32(PMU_BASE + PMU_PLL_LOCK_CNT, 0x180); in pmu_stable_count_config()
100 mmio_write_32(PMU_BASE + PMU_DSU_PWRUP_CNT, 0x180); in pmu_stable_count_config()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/pmu/
H A Dpmu.c67 (mmio_read_32(PMU_BASE + PMU2_CLUSTER_PWR_ST) & BIT(cpu)) == 0 && in check_cpu_wfie()
76 mmio_read_32(PMU_BASE + PMU2_CLUSTER_PWR_ST)); in check_cpu_wfie()
85 return !!(mmio_read_32(PMU_BASE + PMU2_CLUSTER_PWR_ST) & in cpu_power_domain_st()
94 mmio_write_32(PMU_BASE + PMU2_CPU_PWR_SFTCON(cpu), in cpu_power_domain_ctr()
115 if ((mmio_read_32(PMU_BASE + PMU2_CPU_PWR_SFTCON(cpu_id)) & BIT(0)) != 0) in get_cpus_pwr_domain_cfg_info()
118 val = mmio_read_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id)); in get_cpus_pwr_domain_cfg_info()
150 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in cpus_power_domain_on()
163 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in cpus_power_domain_on()
183 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in cpus_power_domain_off()
197 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in cpus_power_domain_off()
[all …]
H A Dpmu.h560 (!!(mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST) & BIT(id)))
563 (!!(mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ACK) & BIT(id)))
H A Dpm_pd_regs.c181 uint32_t pmu_pd_st = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST); in qos_save()
263 uint32_t pmu_pd_st = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST); in qos_restore()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/m0/src/
H A Dsuspend.c25 status_value = mmio_read_32(PMU_BASE + PMU_POWER_ST); in m0_main()
27 mmio_clrbits_32(PMU_BASE + PMU_PWRMODE_CON, 0x01); in m0_main()
44 status_value = mmio_read_32(PMU_BASE + PMU_POWER_ST); in m0_main()
46 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, 0x02); in m0_main()
53 status_value = mmio_read_32(PMU_BASE + PMU_POWER_ST); in m0_main()
55 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, 0x02); in m0_main()
H A Ddram.c21 mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, in idle_port()
23 while ((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & in idle_port()
31 mmio_clrbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, in deidle_port()
33 while (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & in deidle_port()
/rk3399_ARM-atf/plat/rockchip/rk3368/drivers/pmu/
H A Dpmu.c33 regs_updata_bit_set(PMU_BASE + PMU_SFT_CON, pmu_sft_l2flsh_clst_b); in rk3368_flash_l2_b()
36 while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) in rk3368_flash_l2_b()
41 mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST)); in rk3368_flash_l2_b()
44 regs_updata_bit_clr(PMU_BASE + PMU_SFT_CON, pmu_sft_l2flsh_clst_b); in rk3368_flash_l2_b()
146 val = mmio_read_32(PMU_BASE + PMU_BUS_IDE_REQ); in rk3368_pmu_bus_idle()
152 mmio_write_32(PMU_BASE + PMU_BUS_IDE_REQ, val); in rk3368_pmu_bus_idle()
154 while ((mmio_read_32(PMU_BASE + in rk3368_pmu_bus_idle()
159 mmio_read_32(PMU_BASE + PMU_BUS_IDE_ST), in rk3368_pmu_bus_idle()
168 regs_updata_bit_clr(PMU_BASE + PMU_SFT_CON, pmu_sft_acinactm_clst_b); in pmu_scu_b_pwrup()
176 if ((mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & in pmu_scu_b_pwrdn()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/pmu/
H A Dpmu.c253 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_SFTCON(bus / 16), in pmu_bus_idle_req()
266 mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST(bus / 32))); in pmu_bus_idle_req()
276 mmio_write_32(PMU_BASE + PMU2_QCHANNEL_PWR_SFTCON, in pmu_qch_pwr_ctlr()
279 while ((mmio_read_32(PMU_BASE + PMU2_QCHANNEL_STATUS) & msk) != state) { in pmu_qch_pwr_ctlr()
288 mmio_read_32(PMU_BASE + PMU2_QCHANNEL_STATUS)); in pmu_qch_pwr_ctlr()
293 return mmio_read_32(PMU_BASE + PMU2_PWR_CHAIN1_ST(pd / 32)) & BIT(pd % 32) ? in pmu_power_domain_chain_st()
300 return mmio_read_32(PMU_BASE + PMU2_PWR_MEM_ST(pd / 32)) & BIT(pd % 32) ? in pmu_power_domain_mem_st()
310 return mmio_read_32(PMU_BASE + PMU2_BISR_STATUS(4)) & BIT(pd_repair) ? in pmu_power_domain_st()
314 return mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(pd / 32)) & BIT(pd % 32) ? in pmu_power_domain_st()
422 mmio_write_32(PMU_BASE + PMU2_MEMPWR_GATE_SFTCON(pd / 16), in pmu_power_domain_reset_mem()
[all …]
H A Dpmu.h583 (!!(mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST((id) / 32)) & BIT((id) % 32)))
586 (!!(mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ACK((id) / 32)) & BIT((id) % 32)))
/rk3399_ARM-atf/plat/rockchip/px30/drivers/pmu/
H A Dpmu.c126 return mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & BIT(pd) ? in pmu_power_domain_st()
138 mmio_write_32(PMU_BASE + PMU_PWRDN_CON, in pmu_power_domain_ctr()
159 return !!((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & BIT(bus)) && in pmu_bus_idle_st()
160 (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & BIT(bus + 16))); in pmu_bus_idle_st()
167 mmio_write_32(PMU_BASE + PMU_BUS_IDLE_REQ, in pmu_bus_idle_req()
178 __func__, mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST), bus); in pmu_bus_idle_req()
325 pmu_powerdomain_state = mmio_read_32(PMU_BASE + PMU_PWRDN_ST); in pmu_power_domains_suspend()
396 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
399 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
419 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3288/drivers/pmu/
H A Dpmu.c86 mmio_write_32(PMU_BASE + PMU_WAKEUP_CFG1, in pmu_set_sleep_mode()
96 mmio_write_32(PMU_BASE + PMU_STABL_CNT, 32 * 30); in pmu_set_sleep_mode()
99 mmio_write_32(PMU_BASE + PMU_OSC_CNT, in pmu_set_sleep_mode()
109 mmio_write_32(PMU_BASE + PMU_WAKEUP_CFG1, in pmu_set_sleep_mode()
114 mmio_write_32(PMU_BASE + PMU_STABL_CNT, 24000 * 30); in pmu_set_sleep_mode()
117 mmio_write_32(PMU_BASE + PMU_OSC_CNT, 0); in pmu_set_sleep_mode()
120 mmio_write_32(PMU_BASE + PMU_PWRMODE_CON, mode_set); in pmu_set_sleep_mode()
121 mmio_write_32(PMU_BASE + PMU_PWRMODE_CON1, mode_set1); in pmu_set_sleep_mode()
233 mmio_write_32(PMU_BASE + PMU_PWRMODE_CON, store_pmu_pwrmode_con); in rockchip_soc_sys_pwr_dm_resume()
258 store_pmu_pwrmode_con = mmio_read_32(PMU_BASE + PMU_PWRMODE_CON); in rockchip_soc_sys_pwr_dm_suspend()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pmu/
H A Dpmu.c83 mmio_clrsetbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, bus_id, bus_req); in pmu_bus_idle_req()
86 bus_state = mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & bus_id; in pmu_bus_idle_req()
87 bus_ack = mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ACK) & bus_id; in pmu_bus_idle_req()
97 mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST), in pmu_bus_idle_req()
100 mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ACK), in pmu_bus_idle_req()
334 pmu_powerdomain_state = mmio_read_32(PMU_BASE + PMU_PWRDN_ST); in pmu_power_domains_suspend()
426 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B)); in rk3399_flush_l2_b()
433 while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) & in rk3399_flush_l2_b()
441 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B)); in rk3399_flush_l2_b()
448 if ((mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & in pmu_scu_b_pwrdn()
[all …]
H A Dplat_pmu_macros.S89 mov x5, PMU_BASE
116 mov x5, PMU_BASE
/rk3399_ARM-atf/plat/rockchip/common/drivers/pmu/
H A Dpmu_com.h11 #define CHECK_CPU_WFIE_BASE (PMU_BASE + PMU_CORE_PWR_ST)
38 uint32_t pwrdn_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & BIT(pd); in pmu_power_domain_st()
54 val = mmio_read_32(PMU_BASE + PMU_PWRDN_CON); in pmu_power_domain_ctr()
60 mmio_write_32(PMU_BASE + PMU_PWRDN_CON, val); in pmu_power_domain_ctr()
/rk3399_ARM-atf/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c40 pd_reg = mmio_read_32(PMU_BASE + PMU_PWRDN_CON) & BIT(cpu_id); in get_cpus_pwr_domain_cfg_info()
41 apm_reg = mmio_read_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id)) & in get_cpus_pwr_domain_cfg_info()
63 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
68 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
79 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_on()
98 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_off()
106 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), in cpus_power_domain_off()
179 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), CORES_PM_DISABLE); in rockchip_soc_cores_pwr_dm_on_finish()
188 mmio_write_32(PMU_BASE + PMU_CPUAPM_CON(cpu_id), CORES_PM_DISABLE); in rockchip_soc_cores_pwr_dm_resume()
509 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(0)); in ddr_suspend()
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3368/
H A Drk3368_def.h31 #define PMU_BASE 0xff730000 macro
/rk3399_ARM-atf/plat/rockchip/rk3568/
H A Drk3568_def.h49 #define PMU_BASE 0xfdd90000 macro
/rk3399_ARM-atf/plat/rockchip/rk3288/
H A Drk3288_def.h54 #define PMU_BASE 0xff730000 macro
/rk3399_ARM-atf/plat/rockchip/rk3328/
H A Drk3328_def.h27 #define PMU_BASE 0xff140000 macro
/rk3399_ARM-atf/plat/rockchip/px30/
H A Dpx30_def.h21 #define PMU_BASE 0xff000000 macro
/rk3399_ARM-atf/plat/rockchip/rk3399/include/shared/
H A Daddressmap_shared.h26 #define PMU_BASE (MMIO_BASE + 0x07310000) macro
/rk3399_ARM-atf/plat/rockchip/rk3588/
H A Drk3588_def.h90 #define PMU_BASE PMU0_BASE macro
/rk3399_ARM-atf/plat/rockchip/rk3576/
H A Drk3576_def.h79 #define PMU_BASE 0x27360000 macro
/rk3399_ARM-atf/plat/rockchip/rk3328/drivers/soc/
H A Dsoc.c28 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE,
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/
H A Dsuspend.c598 mmio_setbits_32(PMU_BASE + PMU_PWRMODE_CON, (1 << 19)); in pctl_start()
600 mmio_setbits_32(PMU_BASE + PMU_PWRMODE_CON, (1 << 23)); in pctl_start()
691 mmio_clrbits_32(PMU_BASE + PMU_BUS_CLR, PMU_CLR_ALIVE); in pmusram_enable_watchdog()

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