Lines Matching refs:PMU_BASE
253 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_SFTCON(bus / 16), in pmu_bus_idle_req()
266 mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST(bus / 32))); in pmu_bus_idle_req()
276 mmio_write_32(PMU_BASE + PMU2_QCHANNEL_PWR_SFTCON, in pmu_qch_pwr_ctlr()
279 while ((mmio_read_32(PMU_BASE + PMU2_QCHANNEL_STATUS) & msk) != state) { in pmu_qch_pwr_ctlr()
288 mmio_read_32(PMU_BASE + PMU2_QCHANNEL_STATUS)); in pmu_qch_pwr_ctlr()
293 return mmio_read_32(PMU_BASE + PMU2_PWR_CHAIN1_ST(pd / 32)) & BIT(pd % 32) ? in pmu_power_domain_chain_st()
300 return mmio_read_32(PMU_BASE + PMU2_PWR_MEM_ST(pd / 32)) & BIT(pd % 32) ? in pmu_power_domain_mem_st()
310 return mmio_read_32(PMU_BASE + PMU2_BISR_STATUS(4)) & BIT(pd_repair) ? in pmu_power_domain_st()
314 return mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(pd / 32)) & BIT(pd % 32) ? in pmu_power_domain_st()
422 mmio_write_32(PMU_BASE + PMU2_MEMPWR_GATE_SFTCON(pd / 16), in pmu_power_domain_reset_mem()
437 mmio_write_32(PMU_BASE + PMU2_MEMPWR_GATE_SFTCON(pd / 16), in pmu_power_domain_reset_mem()
474 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_SFTCON(pd / 16), in pmu_power_domain_ctr()
492 mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(0)), in pmu_power_domain_ctr()
493 mmio_read_32(PMU_BASE + PMU2_BISR_STATUS(4))); in pmu_power_domain_ctr()
595 mmio_read_32(PMU_BASE + PMU2_QCHANNEL_STATUS) & PMU2_QCH_PWR_MSK; in pmu_power_domains_suspend()
596 ddr_data.pmu_pd_st0 = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(0)); in pmu_power_domains_suspend()
597 ddr_data.bus_idle_st0 = mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST(0)); in pmu_power_domains_suspend()
733 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in cpus_power_domain_on()
735 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in cpus_power_domain_on()
749 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in cpus_power_domain_off()
810 tmp = mmio_read_32(PMU_BASE + PMU2_CLUSTER_ST); in nonboot_cpus_off()
844 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in rockchip_soc_cores_pwr_dm_on_finish()
888 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in rockchip_soc_cores_pwr_dm_resume()
950 mmio_read_32(PMU_BASE + PMU1_DDR_PWR_SFTCON(i)); in ddr_sleep_config()
951 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_SFTCON(i), 0x0fff0900); in ddr_sleep_config()
960 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_SFTCON(i), in ddr_sleep_config_restore()
1011 ddr_data.pmu2_vol_gate_con[0] = mmio_read_32(PMU_BASE + PMU2_VOL_GATE_CON(0)); in pmu_sleep_config()
1012 ddr_data.pmu2_vol_gate_con[1] = mmio_read_32(PMU_BASE + PMU2_VOL_GATE_CON(1)); in pmu_sleep_config()
1013 ddr_data.pmu2_vol_gate_con[2] = mmio_read_32(PMU_BASE + PMU2_VOL_GATE_CON(2)); in pmu_sleep_config()
1016 mmio_read_32(PMU_BASE + PMU2_MEMPWR_MD_GATE_SFTCON(0)); in pmu_sleep_config()
1105 mmio_write_32(PMU_BASE + PMU2_CORE_AUTO_PWR_CON(0), 0x00030000); in pmu_sleep_config()
1106 mmio_write_32(PMU_BASE + PMU2_CORE_AUTO_PWR_CON(1), 0x00030000); in pmu_sleep_config()
1107 mmio_write_32(PMU_BASE + PMU2_CORE_PWR_CON(0), in pmu_sleep_config()
1109 mmio_write_32(PMU_BASE + PMU2_CORE_PWR_CON(1), in pmu_sleep_config()
1111 mmio_write_32(PMU_BASE + PMU2_CLUSTER_IDLE_CON, in pmu_sleep_config()
1113 mmio_write_32(PMU_BASE + PMU2_DSU_AUTO_PWR_CON, 0x00030000); in pmu_sleep_config()
1114 mmio_write_32(PMU_BASE + PMU2_DSU_PWR_CON, in pmu_sleep_config()
1117 mmio_write_32(PMU_BASE + PMU1_OSC_STABLE_CNT_THRESH, 24000); in pmu_sleep_config()
1118 mmio_write_32(PMU_BASE + PMU1_STABLE_CNT_THRESH, 24000); in pmu_sleep_config()
1119 mmio_write_32(PMU_BASE + PMU1_WAKEUP_RST_CLR_CNT_THRESH, 24000); in pmu_sleep_config()
1120 mmio_write_32(PMU_BASE + PMU1_PLL_LOCK_CNT_THRESH, 24000); in pmu_sleep_config()
1121 mmio_write_32(PMU_BASE + PMU1_PWM_SWITCH_CNT_THRESH, 24000); in pmu_sleep_config()
1122 mmio_write_32(PMU_BASE + PMU2_CORE0_STABLE_CNT_THRESH, 24000); in pmu_sleep_config()
1123 mmio_write_32(PMU_BASE + PMU2_CORE0_PWRUP_CNT_THRESH, 24000); in pmu_sleep_config()
1124 mmio_write_32(PMU_BASE + PMU2_CORE0_PWRDN_CNT_THRESH, 24000); in pmu_sleep_config()
1125 mmio_write_32(PMU_BASE + PMU2_CORE1_STABLE_CNT_THRESH, 24000); in pmu_sleep_config()
1126 mmio_write_32(PMU_BASE + PMU2_CORE1_PWRUP_CNT_THRESH, 24000); in pmu_sleep_config()
1127 mmio_write_32(PMU_BASE + PMU2_CORE1_PWRDN_CNT_THRESH, 24000); in pmu_sleep_config()
1128 mmio_write_32(PMU_BASE + PMU2_DSU_STABLE_CNT_THRESH, 24000); in pmu_sleep_config()
1129 mmio_write_32(PMU_BASE + PMU2_DSU_PWRUP_CNT_THRESH, 24000); in pmu_sleep_config()
1130 mmio_write_32(PMU_BASE + PMU2_DSU_PWRDN_CNT_THRESH, 24000); in pmu_sleep_config()
1133 mmio_write_32(PMU_BASE + PMU1_INT_MASK_CON, in pmu_sleep_config()
1137 mmio_write_32(PMU_BASE + PMU1_PWR_CON, in pmu_sleep_config()
1141 mmio_write_32(PMU_BASE + PMU1_CRU_PWR_CON, in pmu_sleep_config()
1145 mmio_write_32(PMU_BASE + PMU1_WAKEUP_INT_CON, pmu1_wkup_int_con); in pmu_sleep_config()
1149 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_CON(i), in pmu_sleep_config()
1156 mmio_write_32(PMU_BASE + PMU1_PLLPD_CON(0), in pmu_sleep_config()
1158 mmio_write_32(PMU_BASE + PMU1_PLLPD_CON(1), in pmu_sleep_config()
1162 mmio_write_32(PMU_BASE + PMU2_PWR_CON1, 0x00ff00fe); in pmu_sleep_config()
1165 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(0), in pmu_sleep_config()
1167 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(1), in pmu_sleep_config()
1169 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(2), in pmu_sleep_config()
1171 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(2), in pmu_sleep_config()
1174 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(0), in pmu_sleep_config()
1176 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(1), in pmu_sleep_config()
1178 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(2), in pmu_sleep_config()
1181 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(0), in pmu_sleep_config()
1183 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(1), 0); in pmu_sleep_config()
1184 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(2), in pmu_sleep_config()
1187 mmio_write_32(PMU_BASE + PMU2_QCHANNEL_PWR_CON, in pmu_sleep_config()
1190 mmio_write_32(PMU_BASE + PMU2_MEMPWR_MD_GATE_SFTCON(0), in pmu_sleep_config()
1210 mmio_write_32(PMU_BASE + PMU2_CORE_PWR_CON(0), 0xffff0000); in pmu_sleep_restore()
1211 mmio_write_32(PMU_BASE + PMU2_CORE_PWR_CON(1), 0xffff0000); in pmu_sleep_restore()
1212 mmio_write_32(PMU_BASE + PMU2_CLUSTER_IDLE_CON, 0xffff0000); in pmu_sleep_restore()
1213 mmio_write_32(PMU_BASE + PMU2_DSU_PWR_CON, 0xffff0000); in pmu_sleep_restore()
1214 mmio_write_32(PMU_BASE + PMU2_PWR_CON1, 0xffff0000); in pmu_sleep_restore()
1219 mmio_write_32(PMU_BASE + PMU1_WAKEUP_INT_CON, 0); in pmu_sleep_restore()
1220 mmio_write_32(PMU_BASE + PMU1_PWR_CON, 0xffff0000); in pmu_sleep_restore()
1221 mmio_write_32(PMU_BASE + PMU1_INT_MASK_CON, 0x00010000); in pmu_sleep_restore()
1222 mmio_write_32(PMU_BASE + PMU0_WAKEUP_INT_CON, 0x00010000); in pmu_sleep_restore()
1223 mmio_write_32(PMU_BASE + PMU0_PWR_CON, 0xffff0000); in pmu_sleep_restore()
1225 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(0), in pmu_sleep_restore()
1227 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(1), in pmu_sleep_restore()
1229 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_CON(2), in pmu_sleep_restore()
1232 mmio_write_32(PMU_BASE + PMU2_MEMPWR_MD_GATE_SFTCON(0), in pmu_sleep_restore()
1266 ddr_data.pmu2_bisr_con0 = mmio_read_32(PMU_BASE + PMU2_BISR_CON(0)); in pm_pll_suspend()
1271 mmio_write_32(PMU_BASE + PMU2_BISR_CON(0), BITS_WITH_WMASK(0, 0x1, 0)); in pm_pll_suspend()
1285 mmio_write_32(PMU_BASE + PMU2_BISR_CON(0), WITH_16BITS_WMSK(ddr_data.pmu2_bisr_con0)); in pm_pll_restore()
1377 mmio_write_32(PMU_BASE + PMU2_BISR_CON(1), 0xffffffff); in rockchip_pmu_pd_init()
1378 mmio_write_32(PMU_BASE + PMU2_BISR_CON(2), 0xffffffff); in rockchip_pmu_pd_init()
1379 mmio_write_32(PMU_BASE + PMU2_BISR_CON(3), 0xffffffff); in rockchip_pmu_pd_init()
1435 mmio_write_32(PMU_BASE + PMU2_BIU_AUTO_CON(0), 0xffffffff); in plat_rockchip_pmu_init()
1436 mmio_write_32(PMU_BASE + PMU2_BIU_AUTO_CON(1), 0xffffffff); in plat_rockchip_pmu_init()
1437 mmio_write_32(PMU_BASE + PMU2_BIU_AUTO_CON(2), 0x00070007); in plat_rockchip_pmu_init()