Lines Matching refs:PMU_BASE
67 (mmio_read_32(PMU_BASE + PMU2_CLUSTER_PWR_ST) & BIT(cpu)) == 0 && in check_cpu_wfie()
76 mmio_read_32(PMU_BASE + PMU2_CLUSTER_PWR_ST)); in check_cpu_wfie()
85 return !!(mmio_read_32(PMU_BASE + PMU2_CLUSTER_PWR_ST) & in cpu_power_domain_st()
94 mmio_write_32(PMU_BASE + PMU2_CPU_PWR_SFTCON(cpu), in cpu_power_domain_ctr()
115 if ((mmio_read_32(PMU_BASE + PMU2_CPU_PWR_SFTCON(cpu_id)) & BIT(0)) != 0) in get_cpus_pwr_domain_cfg_info()
118 val = mmio_read_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id)); in get_cpus_pwr_domain_cfg_info()
150 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in cpus_power_domain_on()
163 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in cpus_power_domain_on()
183 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in cpus_power_domain_off()
197 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in cpus_power_domain_off()
233 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in rockchip_soc_cores_pwr_dm_on_finish()
259 mmio_write_32(PMU_BASE + PMU2_CPU_AUTO_PWR_CON(cpu_id), in rockchip_soc_cores_pwr_dm_resume()
283 mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST) & BIT(pmu_pd_vop) ? 0x3 : 0x7; in ddr_resume()
294 while ((mmio_read_32(PMU_BASE + PMU1_PWR_FSM) & 0xf) != 0) in ddr_resume()
406 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_SFTCON(bus / 16), in pmu_bus_idle_req()
419 mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST)); in pmu_bus_idle_req()
424 return mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST) & BIT(pd) ? in pmu_power_domain_st()
434 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_SFTCON(pd / 16), in pmu_power_domain_ctr()
445 mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST)); in pmu_power_domain_ctr()
541 ddr_data.pmu_pd_st = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST); in pmu_power_domains_suspend()
542 ddr_data.bus_idle_st = mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST); in pmu_power_domains_suspend()
543 ddr_data.pmu2_pwrgt_sft_con0 = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_SFTCON(0)); in pmu_power_domains_suspend()
566 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_SFTCON(0), in pmu_power_domains_resume()
618 uint32_t pmu_pd_st = mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST); in pmu_sleep_config()
619 uint32_t bus_idle_st = mmio_read_32(PMU_BASE + PMU2_BUS_IDLE_ST); in pmu_sleep_config()
621 ddr_data.pmu2_bisr_glb_con = mmio_read_32(PMU_BASE + PMU2_BISR_GLB_CON); in pmu_sleep_config()
624 mmio_read_32(PMU_BASE + PMU2_FAST_POWER_CON); in pmu_sleep_config()
627 mmio_read_32(PMU_BASE + PMU2_C0_PWRACK_BYPASS_CON(0)); in pmu_sleep_config()
629 mmio_read_32(PMU_BASE + PMU2_C1_PWRACK_BYPASS_CON(0)); in pmu_sleep_config()
631 mmio_read_32(PMU_BASE + PMU2_C2_PWRACK_BYPASS_CON(0)); in pmu_sleep_config()
685 mmio_write_32(PMU_BASE + PMU2_BUS_IDLEACK_BYPASS_CON, 0x00030003); in pmu_sleep_config()
689 mmio_write_32(PMU_BASE + PMU2_BISR_GLB_CON, 0x00010000); in pmu_sleep_config()
702 mmio_write_32(PMU_BASE + PMU0_PMIC_STABLE_CNT_THRES, 24000 * 5); in pmu_sleep_config()
703 mmio_write_32(PMU_BASE + PMU0_OSC_STABLE_CNT_THRES, 24000 * 5); in pmu_sleep_config()
705 mmio_write_32(PMU_BASE + PMU1_OSC_STABLE_CNT_THRESH, 24000 * 5); in pmu_sleep_config()
706 mmio_write_32(PMU_BASE + PMU1_STABLE_CNT_THRESH, 24000 * 5); in pmu_sleep_config()
708 mmio_write_32(PMU_BASE + PMU1_SLEEP_CNT_THRESH, 24000 * 15); in pmu_sleep_config()
714 mmio_write_32(PMU_BASE + PMU0_WAKEUP_RST_CLR_CNT_THRES, 12000); in pmu_sleep_config()
716 mmio_write_32(PMU_BASE + PMU1_WAKEUP_RST_CLR_CNT_THRESH, 12000); in pmu_sleep_config()
717 mmio_write_32(PMU_BASE + PMU1_PLL_LOCK_CNT_THRESH, 12000); in pmu_sleep_config()
718 mmio_write_32(PMU_BASE + PMU1_PWM_SWITCH_CNT_THRESH, in pmu_sleep_config()
721 mmio_write_32(PMU_BASE + PMU2_SCU0_PWRUP_CNT_THRESH, 0); in pmu_sleep_config()
722 mmio_write_32(PMU_BASE + PMU2_SCU0_PWRDN_CNT_THRESH, 0); in pmu_sleep_config()
723 mmio_write_32(PMU_BASE + PMU2_SCU0_STABLE_CNT_THRESH, 0); in pmu_sleep_config()
725 mmio_write_32(PMU_BASE + PMU2_FAST_PWRUP_CNT_THRESH_0, 0); in pmu_sleep_config()
726 mmio_write_32(PMU_BASE + PMU2_FAST_PWRDN_CNT_THRESH_0, 0); in pmu_sleep_config()
727 mmio_write_32(PMU_BASE + PMU2_FAST_PWRUP_CNT_THRESH_1, 0); in pmu_sleep_config()
728 mmio_write_32(PMU_BASE + PMU2_FAST_PWRDN_CNT_THRESH_1, 0); in pmu_sleep_config()
729 mmio_write_32(PMU_BASE + PMU2_FAST_PWRUP_CNT_THRESH_2, 0); in pmu_sleep_config()
730 mmio_write_32(PMU_BASE + PMU2_FAST_PWRDN_CNT_THRESH_2, 0); in pmu_sleep_config()
731 mmio_write_32(PMU_BASE + PMU2_FAST_POWER_CON, 0xffff0007); in pmu_sleep_config()
734 mmio_write_32(PMU_BASE + PMU2_CLUSTER0_IDLE_CON, 0xffff0007); in pmu_sleep_config()
735 mmio_write_32(PMU_BASE + PMU2_CLUSTER1_IDLE_CON, 0xffff0007); in pmu_sleep_config()
739 mmio_write_32(PMU_BASE + PMU2_SCU0_PWR_CON, 0xffff020f); in pmu_sleep_config()
740 mmio_write_32(PMU_BASE + PMU2_SCU1_PWR_CON, 0xffff020f); in pmu_sleep_config()
741 mmio_write_32(PMU_BASE + PMU2_SCU0_AUTO_PWR_CON, 0x00070000); in pmu_sleep_config()
742 mmio_write_32(PMU_BASE + PMU2_SCU1_AUTO_PWR_CON, 0x00070000); in pmu_sleep_config()
744 mmio_write_32(PMU_BASE + PMU2_CCI_PWR_CON, 0xffff0009); in pmu_sleep_config()
750 mmio_write_32(PMU_BASE + PMU1_PWR_CON, WITH_16BITS_WMSK(pmu1_pwr_con)); in pmu_sleep_config()
753 mmio_write_32(PMU_BASE + PMU1_CRU_PWR_CON(0), WITH_16BITS_WMSK(pmu1cru_pwr_con)); in pmu_sleep_config()
756 mmio_write_32(PMU_BASE + PMU0_DDR_RET_CON(1), 0xffff0000); in pmu_sleep_config()
757 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_CON(0), WITH_16BITS_WMSK(pmu1_ddr_pwr_con)); in pmu_sleep_config()
758 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_CON(1), WITH_16BITS_WMSK(pmu1_ddr_pwr_con)); in pmu_sleep_config()
759 mmio_write_32(PMU_BASE + PMU1_DDR_AXIPWR_CON(0), 0x03ff03ff); in pmu_sleep_config()
760 mmio_write_32(PMU_BASE + PMU1_DDR_AXIPWR_CON(1), 0x03ff03ff); in pmu_sleep_config()
763 mmio_write_32(PMU_BASE + PMU1_PLLPD_CON(0), WITH_16BITS_WMSK(pmu1_pll_pd_con)); in pmu_sleep_config()
766 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(0), WITH_16BITS_WMSK(pmu2_bus_idle_con[0])); in pmu_sleep_config()
767 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(1), WITH_16BITS_WMSK(pmu2_bus_idle_con[1])); in pmu_sleep_config()
770 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(0), WITH_16BITS_WMSK(pmu2_pwr_gt_con[0])); in pmu_sleep_config()
771 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(1), WITH_16BITS_WMSK(pmu2_pwr_gt_con[1])); in pmu_sleep_config()
774 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_SFTCON(0), 0xffff0031); in pmu_sleep_config()
775 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_SFTCON(1), 0xffff0200); in pmu_sleep_config()
778 mmio_write_32(PMU_BASE + PMU1_WAKEUP_INT_CON, pmu1_wkup_int_con); in pmu_sleep_config()
788 mmio_write_32(PMU_BASE + PMU2_C0_PWRACK_BYPASS_CON(0), 0x01000100); in pmu_sleep_config()
789 mmio_write_32(PMU_BASE + PMU2_C1_PWRACK_BYPASS_CON(0), 0x01000100); in pmu_sleep_config()
790 mmio_write_32(PMU_BASE + PMU2_C2_PWRACK_BYPASS_CON(0), 0x01000100); in pmu_sleep_config()
795 mmio_write_32(PMU_BASE + PMU0_INFO_TX_CON, 0xffff0000); in pmu_sleep_restore()
796 mmio_write_32(PMU_BASE + PMU2_DEBUG_INFO_SEL, 0xffff0000); in pmu_sleep_restore()
797 mmio_write_32(PMU_BASE + PMU2_CLUSTER0_IDLE_CON, 0xffff0000); in pmu_sleep_restore()
798 mmio_write_32(PMU_BASE + PMU2_SCU0_PWR_CON, 0xffff0000); in pmu_sleep_restore()
799 mmio_write_32(PMU_BASE + PMU2_CCI_PWR_CON, 0xffff0000); in pmu_sleep_restore()
800 mmio_write_32(PMU_BASE + PMU1_INT_MASK_CON, 0xffff0000); in pmu_sleep_restore()
801 mmio_write_32(PMU_BASE + PMU1_PWR_CON, 0xffff0000); in pmu_sleep_restore()
802 mmio_write_32(PMU_BASE + PMU1_CRU_PWR_CON(0), 0xffff0000); in pmu_sleep_restore()
803 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_CON(0), 0xffff0000); in pmu_sleep_restore()
804 mmio_write_32(PMU_BASE + PMU1_DDR_PWR_CON(1), 0xffff0000); in pmu_sleep_restore()
805 mmio_write_32(PMU_BASE + PMU1_DDR_AXIPWR_CON(0), 0xffff0000); in pmu_sleep_restore()
806 mmio_write_32(PMU_BASE + PMU1_DDR_AXIPWR_CON(1), 0xffff0000); in pmu_sleep_restore()
807 mmio_write_32(PMU_BASE + PMU1_PLLPD_CON(0), 0xffff0000); in pmu_sleep_restore()
808 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(0), 0xffff0000); in pmu_sleep_restore()
809 mmio_write_32(PMU_BASE + PMU2_BUS_IDLE_CON(1), 0xffff0000); in pmu_sleep_restore()
810 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(0), 0xffff0000); in pmu_sleep_restore()
811 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_CON(1), 0xffff0000); in pmu_sleep_restore()
812 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_SFTCON(0), 0xffff0000); in pmu_sleep_restore()
813 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_SFTCON(1), 0xffff0000); in pmu_sleep_restore()
814 mmio_write_32(PMU_BASE + PMU2_BUS_IDLEACK_BYPASS_CON, 0xffff0000); in pmu_sleep_restore()
815 mmio_write_32(PMU_BASE + PMU1_WAKEUP_INT_CON, 0); in pmu_sleep_restore()
816 mmio_write_32(PMU_BASE + PMU2_FAST_POWER_CON, in pmu_sleep_restore()
818 mmio_write_32(PMU_BASE + PMU2_BISR_GLB_CON, in pmu_sleep_restore()
821 mmio_write_32(PMU_BASE + PMU2_C0_PWRACK_BYPASS_CON(0), in pmu_sleep_restore()
823 mmio_write_32(PMU_BASE + PMU2_C1_PWRACK_BYPASS_CON(0), in pmu_sleep_restore()
825 mmio_write_32(PMU_BASE + PMU2_C2_PWRACK_BYPASS_CON(0), in pmu_sleep_restore()
1017 mmio_write_32(PMU_BASE + PMU2_BISR_PDGEN_CON(1), in rockchip_pmu_pd_repair_init()
1041 mmio_write_32(PMU_BASE + PMU2_NOC_AUTO_CON(0), 0xffffffff); in plat_rockchip_pmu_init()
1042 mmio_write_32(PMU_BASE + PMU2_NOC_AUTO_CON(1), 0xffffffff); in plat_rockchip_pmu_init()
1048 mmio_write_32(PMU_BASE + PMU2_VOL_GATE_SFTCON(0), in plat_rockchip_pmu_init()