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Searched refs:PMUCRU_BASE (Results 1 – 12 of 12) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pmu/
H A Dm0_ctl.c27 mmio_setbits_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, 0x02); in m0_init()
37 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKSEL_CON0, in m0_init()
40 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, WMSK_BIT(5)); in m0_init()
57 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, in m0_start()
64 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, in m0_start()
69 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, in m0_start()
77 mmio_write_32(PMUCRU_BASE + PMUCRU_SOFTRST_CON0, in m0_stop()
81 mmio_write_32(PMUCRU_BASE + PMUCRU_CLKGATE_CON2, in m0_stop()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/soc/
H A Dsoc.c56 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE); in set_pll_slow_mode()
65 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_NOMAL_MODE); in set_pll_normal_mode()
74 mmio_write_32(PMUCRU_BASE + in set_pll_bypass()
187 mmio_read_32(PMUCRU_BASE + PMUCRU_GATE_CON(i)); in clk_gate_con_save()
199 mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i), REG_SOC_WMSK); in clk_gate_con_disable()
210 mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i), in clk_gate_con_restore()
221 mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), in set_plls_nobypass()
239 pmu_slp_data.pmucru_rstnhold_con0 = mmio_read_32(PMUCRU_BASE + in set_pmu_rsthold()
241 pmu_slp_data.pmucru_rstnhold_con1 = mmio_read_32(PMUCRU_BASE + in set_pmu_rsthold()
263 mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON0, rstnhold_cofig0); in set_pmu_rsthold()
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/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/m0/src/
H A Ddram.c18 gatedis_con0 = mmio_read_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0); in idle_port()
19 mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, 0x3fffffff); in idle_port()
38 mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, gatedis_con0); in deidle_port()
/rk3399_ARM-atf/plat/rockchip/px30/drivers/soc/
H A Dsoc.c56 mmio_read_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i)); in clk_gate_con_save()
69 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i), in clk_gate_con_restore()
82 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i), in clk_gate_con_disable()
/rk3399_ARM-atf/plat/rockchip/px30/drivers/pmu/
H A Dpmu.c557 mmio_read_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i)); in clk_gate_suspend()
558 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i), in clk_gate_suspend()
568 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATES_CON(i), in clk_gate_resume()
581 mmio_read_32(PMUCRU_BASE + CRU_PMU_CLKSELS_CON(0)); in pvtm_32k_config()
629 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKSELS_CON(0), in pvtm_32k_config()
635 mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKSELS_CON(0), in pvtm_32k_config_restore()
877 mmio_write_32(PMUCRU_BASE + CRU_PMU_MODE, in pll_set_mode()
889 pll_base = PMUCRU_BASE + CRU_PLL_CONS(0, 0); in pll_suspend()
908 pll_base = PMUCRU_BASE + CRU_PLL_CONS(0, 0); in pll_resume()
922 ddr_data.cru_pmu_mode_save = mmio_read_32(PMUCRU_BASE + CRU_PMU_MODE); in pm_plls_suspend()
/rk3399_ARM-atf/plat/rockchip/rk3568/
H A Drk3568_def.h38 #define PMUCRU_BASE 0xfdd00000 macro
/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/soc/
H A Dsoc.c75 mmio_write_32(PMUCRU_BASE + PMUCRU_MODE_CON00, 0x000f0000); in soc_global_soft_reset()
/rk3399_ARM-atf/plat/rockchip/px30/
H A Dpx30_def.h100 #define PMUCRU_BASE 0xff2bc000 macro
/rk3399_ARM-atf/plat/rockchip/rk3399/include/shared/
H A Daddressmap_shared.h37 #define PMUCRU_BASE (MMIO_BASE + 0x07750000) macro
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/gpio/
H A Drk3399_gpio.c79 .clkgate_reg = PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1),
86 .clkgate_reg = PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1),
/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/pmu/
H A Dpmu.c281 mmio_write_32(PMUCRU_BASE + PMUCRU_PMUGATE_CON01, 0x38000000); in pvtm_32k_config()
308 mmio_write_32(PMUCRU_BASE + PMUCRU_PMUCLKSEL_CON00, 0x00c00000); in pvtm_32k_config()
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/dram/
H A Dsuspend.c482 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), in dram_all_config()