56 		mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE);  in set_pll_slow_mode()
65 		mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_NOMAL_MODE);  in set_pll_normal_mode()
74 		mmio_write_32(PMUCRU_BASE +  in set_pll_bypass()
187 			mmio_read_32(PMUCRU_BASE + PMUCRU_GATE_CON(i));  in clk_gate_con_save()
199 		mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i), REG_SOC_WMSK);  in clk_gate_con_disable()
210 		mmio_write_32(PMUCRU_BASE + PMUCRU_GATE_CON(i),  in clk_gate_con_restore()
221 		mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3),  in set_plls_nobypass()
239 	pmu_slp_data.pmucru_rstnhold_con0 = mmio_read_32(PMUCRU_BASE +  in set_pmu_rsthold()
241 	pmu_slp_data.pmucru_rstnhold_con1 = mmio_read_32(PMUCRU_BASE +  in set_pmu_rsthold()
263 	mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON0, rstnhold_cofig0);  in set_pmu_rsthold()
264 	mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON1, rstnhold_cofig1);  in set_pmu_rsthold()
269 	mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1),  in pmu_sgrf_rst_hld()
284 	mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1),  in pmu_sgrf_rst_hld_release()
290 	mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON0,  in restore_pmu_rsthold()
292 	mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON1,  in restore_pmu_rsthold()
322 	mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1),  in soc_global_soft_reset_init()