Home
last modified time | relevance | path

Searched refs:GICV2_INTR_GROUP0 (Results 1 – 25 of 34) sorted by relevance

12

/rk3399_ARM-atf/plat/qti/msm8916/
H A Dmsm8916_gicv2.c26 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
28 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
30 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
32 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
34 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
36 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
38 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
40 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
42 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
/rk3399_ARM-atf/plat/amlogic/gxbb/
H A Dgxbb_bl31_setup.c108 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
110 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
112 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
114 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
116 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
118 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
120 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
122 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
124 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
/rk3399_ARM-atf/plat/renesas/common/aarch64/
H A Dplatform_common.c230 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
233 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
235 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
237 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
239 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
241 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
243 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
245 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
247 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
249 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
[all …]
/rk3399_ARM-atf/plat/amlogic/g12a/
H A Dg12a_bl31_setup.c108 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
110 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
112 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
114 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
116 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
118 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
120 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
122 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
124 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
/rk3399_ARM-atf/plat/amlogic/gxl/
H A Dgxl_bl31_setup.c144 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
146 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
148 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
150 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
152 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
154 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
156 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
158 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
160 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
/rk3399_ARM-atf/plat/amlogic/axg/
H A Daxg_bl31_setup.c134 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
136 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
138 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
140 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
142 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
144 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
146 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
148 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
150 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
/rk3399_ARM-atf/plat/qemu/common/
H A Dqemu_gicv2.c12 PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0),
13 PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
/rk3399_ARM-atf/plat/hisilicon/poplar/
H A Dpoplar_gicv2.c17 POPLAR_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
18 POPLAR_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
/rk3399_ARM-atf/drivers/arm/gic/v2/
H A Dgicv2_base.c23 PLAT_ARM_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
24 PLAT_ARM_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
H A Dgicv2_helpers.c141 assert(prop_desc->intr_grp == GICV2_INTR_GROUP0); in gicv2_secure_spis_configure_props()
194 assert(prop_desc->intr_grp == GICV2_INTR_GROUP0); in gicv2_secure_ppi_sgi_setup_props()
/rk3399_ARM-atf/plat/common/
H A Dplat_gicv2_base.c27 PLAT_ARM_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
28 PLAT_ARM_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
/rk3399_ARM-atf/plat/st/common/
H A Dstm32mp_gic.c28 PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0),
29 PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
/rk3399_ARM-atf/plat/rockchip/rk3288/
H A Drk3288_def.h123 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \
125 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t210/
H A Dplat_setup.c192 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
194 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
196 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
/rk3399_ARM-atf/plat/marvell/armada/common/
H A Dmarvell_gicv2.c46 PLAT_MARVELL_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
47 PLAT_MARVELL_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
/rk3399_ARM-atf/plat/rockchip/rk3328/
H A Drk3328_def.h143 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \
145 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
/rk3399_ARM-atf/plat/hisilicon/hikey/
H A Dhikey_bl31_setup.c38 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
40 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
/rk3399_ARM-atf/plat/qemu/common/sp_min/
H A Dsp_min_setup.c55 PLATFORM_G1S_PROPS(GICV2_INTR_GROUP0),
56 PLATFORM_G0_PROPS(GICV2_INTR_GROUP0)
/rk3399_ARM-atf/plat/rockchip/px30/
H A Dpx30_def.h165 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \
167 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
/rk3399_ARM-atf/plat/nuvoton/common/
H A Dplat_nuvoton_gic.c16 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
/rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/
H A Dplat_setup.c237 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
239 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
241 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
/rk3399_ARM-atf/plat/intel/soc/n5x/
H A Dbl31_plat_setup.c87 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
88 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
/rk3399_ARM-atf/plat/intel/soc/stratix10/
H A Dbl31_plat_setup.c94 PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
95 PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
/rk3399_ARM-atf/plat/rockchip/rk3576/
H A Drk3576_def.h188 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), \
190 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)
/rk3399_ARM-atf/plat/rockchip/rk3368/
H A Drk3368_def.h114 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL)

12