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Searched refs:CPU0 (Results 1 – 19 of 19) sorted by relevance

/rk3399_ARM-atf/fdts/
H A Drdaspen-defs.dtsi73 #define CLUSTER_0_DSU_PMU_CPU_LIST <&CPU0>
81 #define CLUSTER_0_DSU_PMU_CPU_LIST <&CPU0>, <&CPU1>
91 #define CLUSTER_0_DSU_PMU_CPU_LIST <&CPU0>, <&CPU1>, <&CPU2>
103 #define CLUSTER_0_DSU_PMU_CPU_LIST <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>
H A Drdv3-defs.dtsi21 CPU0:cpu@0 { \ label
H A Dmorello-fvp.dts61 cpu = <&CPU0>;
76 CPU0: cpu0@0 { label
H A Dtc-base.dtsi76 cpu = <&CPU0>;
127 CPU0:cpu@0 { label
592 cpu = <&CPU0>;
719 affinity = <&CPU0>, <&CPU1>;
757 cpus = <&CPU0>, <&CPU1>, <&CPU2>, <&CPU3>, <&CPU4>, <&CPU5>, <&CPU6>, <&CPU7>;
H A Dfvp-base-gicv5.dtsi33 cpus = <&CPU0
H A Dfvp-defs.dtsi53 CPU0:cpu@0 { \ label
/rk3399_ARM-atf/plat/intel/soc/common/soc/
H A Dsocfpga_firewall.c120 mmio_clrbits_32(SOCFPGA_CCU_NOC(CPU0, RAM0), in enable_ns_ocram_access()
134 mmio_setbits_32(SOCFPGA_CCU_NOC(CPU0, RAM0), in enable_ocram_firewall()
/rk3399_ARM-atf/docs/plat/
H A Dmeson-axg.rst11 - Basic PSCI support (CPU_ON, CPU_OFF, SYSTEM_RESET, SYSTEM_OFF). Note that CPU0
H A Dmeson-gxbb.rst11 - Basic PSCI support (CPU_ON, CPU_OFF, SYSTEM_RESET, SYSTEM_OFF). Note that CPU0
H A Dmeson-g12a.rst11 - Basic PSCI support (CPU_ON, CPU_OFF, SYSTEM_RESET, SYSTEM_OFF). Note that CPU0
H A Dmeson-gxl.rst11 - Basic PSCI support (CPU_ON, CPU_OFF, SYSTEM_RESET, SYSTEM_OFF). Note that CPU0
H A Dpoplar.rst116 LOADER: CPU0 executes at 0x000ce000
/rk3399_ARM-atf/plat/arm/board/tc/fdts/
H A Dtc_spmc_manifest.dtsi32 CPU0:cpu@0 { label
/rk3399_ARM-atf/plat/marvell/armada/a8k/common/
H A Dplat_pm.c68 CPU0, enumerator
/rk3399_ARM-atf/docs/design/
H A Dpsci-pd-tree.rst248 CPU0 | 3 | |
H A Dfirmware-design.rst2314 CPU0 updates its per-CPU field with data cache enabled. This write updates a
2319 the update made by CPU0 as well.
2356 | Lock_0 | for CPU0
2359 | Lock_1 | for CPU0
2364 | Lock_N | for CPU0
2389 operation on Lock_N, the corresponding ``bakery_info_t`` in both CPU0 and CPU1
/rk3399_ARM-atf/docs/design_documents/
H A Dpsci_osi_mode.rst481 CPU0: cpu@0 {
/rk3399_ARM-atf/docs/
H A Dporting-guide.rst2271 - Target all secure SPIs to CPU0.
H A Dchange-log.md10942 - mediatek: mt8183: Fix AARCH64 init fail on CPU0