1afd241e7SCarlo CaioneAmlogic Meson A113D (AXG) 2afd241e7SCarlo Caione=========================== 3afd241e7SCarlo Caione 4afd241e7SCarlo CaioneThe Amlogic Meson A113D is a SoC with a quad core Arm Cortex-A53 running at 5afd241e7SCarlo Caione~1.2GHz. It also contains a Cortex-M3 used as SCP. 6afd241e7SCarlo Caione 7afd241e7SCarlo CaioneThis port is a minimal implementation of BL31 capable of booting mainline U-Boot 8afd241e7SCarlo Caioneand Linux: 9afd241e7SCarlo Caione 10afd241e7SCarlo Caione- SCPI support. 11afd241e7SCarlo Caione- Basic PSCI support (CPU_ON, CPU_OFF, SYSTEM_RESET, SYSTEM_OFF). Note that CPU0 12afd241e7SCarlo Caione can't be turned off, so there is a workaround to hide this from the caller. 13afd241e7SCarlo Caione- GICv2 driver set up. 14afd241e7SCarlo Caione- Basic SIP services (read efuse data, enable/disable JTAG). 15afd241e7SCarlo Caione 16afd241e7SCarlo CaioneIn order to build it: 17afd241e7SCarlo Caione 18afd241e7SCarlo Caione.. code:: shell 19afd241e7SCarlo Caione 20afd241e7SCarlo Caione CROSS_COMPILE=aarch64-none-elf- make DEBUG=1 PLAT=axg [SPD=opteed] 2172d2535aSCarlo Caione [AML_USE_ATOS=1 when using ATOS as BL32] 22afd241e7SCarlo Caione 23afd241e7SCarlo CaioneThis port has been tested on a A113D board. After building it, follow the 24afd241e7SCarlo Caioneinstructions in the `U-Boot repository`_, replacing the mentioned **bl31.img** 25afd241e7SCarlo Caioneby the one built from this port. 26afd241e7SCarlo Caione 27*0396bcbcSSandrine Bailleux.. _U-Boot repository: https://github.com/u-boot/u-boot/blob/master/doc/board/amlogic/s400.rst 28