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/rk3399_ARM-atf/plat/arm/board/juno/aarch32/
H A Djuno_helpers.S97 jump_if_cpu_midr CORTEX_A57_MIDR, A57
100 A57: label
/rk3399_ARM-atf/docs/plat/
H A Dnvidia-tegra.rst22 T186 has Dual NVIDIA Denver2 ARM® CPU cores, plus Quad ARM Cortex®-A57 cores,
23 in a coherent multiprocessor configuration. The Denver 2 and Cortex-A57 cores
27 unified cache. The Cortex-A57 processors each have 48 KB Instruction and 32 KB
60 T210 has Quad Arm® Cortex®-A57 cores in a switched configuration with a
61 companion set of quad Arm Cortex-A53 cores. The Cortex-A57 and A53 cores
63 including legacy Armv7-A applications. The Cortex-A57 processors each have
150 Protection bit, for Arm Cortex-A57 CPUs, during CPU boot. This flag will
H A Drz-g2.rst6 Through a variety of Arm Cortex®-A53 and A57-based devices, engineers can
/rk3399_ARM-atf/plat/arm/board/juno/aarch64/
H A Djuno_helpers.S101 jump_if_cpu_midr CORTEX_A57_MIDR, A57
104 A57: label
/rk3399_ARM-atf/plat/renesas/common/aarch64/
H A Dplat_helpers.S362 b.eq A57
364 A57: label
/rk3399_ARM-atf/docs/plat/arm/fvp/
H A Dfvp-cortex-a57-a53.rst1 Running on the Cortex-A57-A53 Base FVP
H A Dfvp-support.rst30 - ``FVP_Base_Cortex-A57``
H A Dfvp-specific-configs.rst207 For use with models such as the Cortex-A57-A53 or Cortex-A32 Base FVPs
212 For use with models such as the Cortex-A57-A53 or Cortex-A32 Base FVPs
/rk3399_ARM-atf/docs/security_advisories/
H A Dsecurity-advisory-tfv-6.rst48 For Cortex-A57 and Cortex-A72 CPUs, the Pull Requests (PRs) in this advisory
75 ``SMCCC_ARCH_WORKAROUND_1`` SMCs on Cortex-A57, using both the "MMU
81 at invalidating the branch predictor on Cortex-A57, the drop into Secure-EL1
H A Dsecurity-advisory-tfv-9.rst110 Cortex-A57, Coxtex-A72, Cortex-A73 and Cortex-A75 using the existing workaround.
H A Dsecurity-advisory-tfv-7.rst65 - Cortex-A57 and Cortex-A72, by setting bit 55 (Disable load pass store) of
/rk3399_ARM-atf/docs/design/
H A Dcpu-specific-build-macros.rst60 is for example ``A57`` for the ``Cortex_A57`` CPU.
167 For Cortex-A57, the following errata build flags are defined :
169 - ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57
172 - ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57
175 - ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57
178 - ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57
181 - ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57
184 - ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57
187 - ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57
190 - ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57
[all …]
/rk3399_ARM-atf/docs/perf/
H A Dpsci-performance-juno.rst13 x Cortex-A57 clusters running at the following frequencies:
18 | Cortex-A57 | 900 (nominal) |
292 CPUs 4-5 refer to CPUs in the big cluster (A57). In all cases CPU 4 is the lead
/rk3399_ARM-atf/docs/
H A Dchange-log.md8591 …- apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57 ([9b2510b](https://review.trustedfirmware.org/p…
8593 …- report CVE 2022 23960 missing for aarch32 A57 and A72 ([2e5d7a4](https://review.trustedfirmware.…
8598 …- workaround for CVE-2022-23960 for Cortex-A57, Cortex-A72 ([be9121f](https://review.trustedfirmwa…
10224 - Arm Cortex-A57
11421 - arm/juno: Enable new CPU errata workarounds for A53 and A57
12138 - Applied workarounds CVE-2017-5715 on Arm Cortex-A57, -A72, -A73 and -A75, and
12141 - Applied errata workaround for Arm Cortex-A57: 859972.
12378 - Applied errata workaround for Arm-Cortex-A57: 813419.
12380 - Enabled all A53 and A57 errata workarounds for Juno, both in AArch64 and
12589 - Applied following erratum workarounds for Cortex-A57: 833471, 826977, 829520,
[all …]
/rk3399_ARM-atf/docs/getting_started/
H A Dbuild-options.rst1282 | 1319537 | Cortex-A57 | ``ERRATA_A57_1319537`` |