docs/design/cpu-specific-build-macros.rst

60 is for example ``A57`` for the ``Cortex_A57`` CPU.
167 For Cortex-A57, the following errata build flags are defined :
169 -  ``ERRATA_A57_806969``: This applies errata 806969 workaround to Cortex-A57
172 -  ``ERRATA_A57_813419``: This applies errata 813419 workaround to Cortex-A57
175 -  ``ERRATA_A57_813420``: This applies errata 813420 workaround to Cortex-A57
178 -  ``ERRATA_A57_814670``: This applies errata 814670 workaround to Cortex-A57
181 -  ``ERRATA_A57_817169``: This applies errata 817169 workaround to Cortex-A57
184 -  ``ERRATA_A57_826974``: This applies errata 826974 workaround to Cortex-A57
187 -  ``ERRATA_A57_826977``: This applies errata 826977 workaround to Cortex-A57
190 -  ``ERRATA_A57_828024``: This applies errata 828024 workaround to Cortex-A57
193 -  ``ERRATA_A57_829520``: This applies errata 829520 workaround to Cortex-A57
196 -  ``ERRATA_A57_833471``: This applies errata 833471 workaround to Cortex-A57
199 -  ``ERRATA_A57_859972``: This applies errata 859972 workaround to Cortex-A57
203    revisions of Cortex-A57 CPU.
1450    Cortex-A57 cluster power down sequence by not flushing the Level 1 data
1453    is a known safe deviation from the Cortex-A57 TRM defined power down
1454    sequence. Each Cortex-A57 based platform must make its own decision on
1467    ``A53_DISABLE_NON_TEMPORAL_HINT`` but for Cortex-A57. This needs to be
1470    `Cortex-A57 Software Optimization Guide`_.
1473    streaming enhancement feature for Cortex-A57 CPUs. Platforms can set
1475    line fill requests from the Cortex-A57 processor are atomic. Each
1476    Cortex-A57 based platform must make its own decision on whether to use
1509 .. _Cortex-A57 Software Optimization Guide: https://developer.arm.com/documentation/uan0015