1*c5407693SSandrine BailleuxRunning on the Cortex-A57-A53 Base FVP 2*c5407693SSandrine Bailleux====================================== 3*c5407693SSandrine Bailleux 4*c5407693SSandrine BailleuxWith reset to BL1 entrypoint 5*c5407693SSandrine Bailleux^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 6*c5407693SSandrine Bailleux 7*c5407693SSandrine BailleuxThe following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to 8*c5407693SSandrine Bailleuxboot Linux with 8 CPUs using the AArch64 build of TF-A. 9*c5407693SSandrine Bailleux 10*c5407693SSandrine Bailleux.. code:: shell 11*c5407693SSandrine Bailleux 12*c5407693SSandrine Bailleux <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ 13*c5407693SSandrine Bailleux -C pctl.startup=0.0.0.0 \ 14*c5407693SSandrine Bailleux -C bp.secure_memory=1 \ 15*c5407693SSandrine Bailleux -C bp.tzc_400.diagnostics=1 \ 16*c5407693SSandrine Bailleux -C cache_state_modelled=1 \ 17*c5407693SSandrine Bailleux -C bp.secureflashloader.fname="<path-to>/<bl1-binary>" \ 18*c5407693SSandrine Bailleux -C bp.flashloader0.fname="<path-to>/<FIP-binary>" \ 19*c5407693SSandrine Bailleux --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 20*c5407693SSandrine Bailleux --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 21*c5407693SSandrine Bailleux 22*c5407693SSandrine BailleuxWith reset to BL31 entrypoint 23*c5407693SSandrine Bailleux^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 24*c5407693SSandrine Bailleux 25*c5407693SSandrine BailleuxThe following ``FVP_Base_Cortex-A57x4-A53x4`` model parameters should be used to 26*c5407693SSandrine Bailleuxboot Linux with 8 CPUs using the AArch64 build of TF-A. 27*c5407693SSandrine Bailleux 28*c5407693SSandrine Bailleux.. code:: shell 29*c5407693SSandrine Bailleux 30*c5407693SSandrine Bailleux <path-to>/FVP_Base_Cortex-A57x4-A53x4 \ 31*c5407693SSandrine Bailleux -C pctl.startup=0.0.0.0 \ 32*c5407693SSandrine Bailleux -C bp.secure_memory=1 \ 33*c5407693SSandrine Bailleux -C bp.tzc_400.diagnostics=1 \ 34*c5407693SSandrine Bailleux -C cache_state_modelled=1 \ 35*c5407693SSandrine Bailleux -C cluster0.cpu0.RVBARADDR=0x04010000 \ 36*c5407693SSandrine Bailleux -C cluster0.cpu1.RVBARADDR=0x04010000 \ 37*c5407693SSandrine Bailleux -C cluster0.cpu2.RVBARADDR=0x04010000 \ 38*c5407693SSandrine Bailleux -C cluster0.cpu3.RVBARADDR=0x04010000 \ 39*c5407693SSandrine Bailleux -C cluster1.cpu0.RVBARADDR=0x04010000 \ 40*c5407693SSandrine Bailleux -C cluster1.cpu1.RVBARADDR=0x04010000 \ 41*c5407693SSandrine Bailleux -C cluster1.cpu2.RVBARADDR=0x04010000 \ 42*c5407693SSandrine Bailleux -C cluster1.cpu3.RVBARADDR=0x04010000 \ 43*c5407693SSandrine Bailleux --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000 \ 44*c5407693SSandrine Bailleux --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000 \ 45*c5407693SSandrine Bailleux --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \ 46*c5407693SSandrine Bailleux --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \ 47*c5407693SSandrine Bailleux --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000 \ 48*c5407693SSandrine Bailleux --data cluster0.cpu0="<path-to>/<ramdisk>"@0x84000000 49*c5407693SSandrine Bailleux 50*c5407693SSandrine Bailleux-------------- 51*c5407693SSandrine Bailleux 52*c5407693SSandrine Bailleux*Copyright (c) 2019-2024, Arm Limited. All rights reserved.* 53