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Searched refs:register_phys_mem (Results 1 – 22 of 22) sorted by relevance

/optee_os/core/arch/arm/plat-hisilicon/
H A Dmain.c16 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, PL011_REG_SIZE);
18 register_phys_mem(MEM_AREA_IO_SEC, BOOTSRAM_BASE, BOOTSRAM_SIZE);
21 register_phys_mem(MEM_AREA_IO_SEC, CPU_CRG_BASE, CPU_CRG_SIZE);
24 register_phys_mem(MEM_AREA_IO_SEC, SYS_CTRL_BASE, SYS_CTRL_SIZE);
/optee_os/core/arch/arm/plat-aspeed/
H A Dplatform_ast2600.c46 register_phys_mem(MEM_AREA_IO_NSEC, CONSOLE_UART_BASE, SMALL_PAGE_SIZE);
47 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE + GICD_OFFSET, GIC_DIST_REG_SIZE);
48 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE + GICC_OFFSET, GIC_CPU_REG_SIZE);
49 register_phys_mem(MEM_AREA_IO_SEC, AHBC_BASE, SMALL_PAGE_SIZE);
50 register_phys_mem(MEM_AREA_IO_NSEC, SCU_BASE, SMALL_PAGE_SIZE);
H A Dplatform_ast2700.c14 register_phys_mem(MEM_AREA_IO_SEC, UART_BASE, SMALL_PAGE_SIZE);
15 register_phys_mem(MEM_AREA_IO_SEC, GICD_BASE, GIC_DIST_REG_SIZE);
16 register_phys_mem(MEM_AREA_IO_SEC, GICR_BASE, GICR_SIZE);
/optee_os/core/arch/arm/plat-bcm/
H A Dmain.c47 register_phys_mem(MEM_AREA_RAM_SEC, BCM_DRAM0_SEC_BASE, BCM_DRAM0_SEC_SIZE);
50 register_phys_mem(MEM_AREA_IO_NSEC, CFG_BCM_ELOG_AP_UART_LOG_BASE,
54 register_phys_mem(MEM_AREA_RAM_NSEC, CFG_BCM_ELOG_BASE, CFG_BCM_ELOG_SIZE);
/optee_os/core/arch/arm/plat-imx/
H A Dmain.c74 register_phys_mem(MEM_AREA_TEE_COHERENT,
79 register_phys_mem(MEM_AREA_IO_SEC, M4_AIPS_BASE, M4_AIPS_SIZE);
82 register_phys_mem(MEM_AREA_TEE_COHERENT,
H A Dtzc380.c27 register_phys_mem(MEM_AREA_IO_SEC, TZASC2_BASE, TZASC_SIZE);
30 register_phys_mem(MEM_AREA_IO_SEC, TZASC_BASE, TZASC_SIZE);
/optee_os/core/arch/arm/plat-telechips/
H A Dmain.c16 register_phys_mem(MEM_AREA_IO_SEC, TCC_IO_BASE, TCC_IO_SIZE);
18 register_phys_mem(MEM_AREA_IO_SEC, TZC_BASE, TZC_SIZE);
/optee_os/core/arch/arm/plat-rzn1/
H A Dmain.c33 register_phys_mem(MEM_AREA_IO_SEC, GIC_BASE, CORE_MMU_PGDIR_SIZE);
34 register_phys_mem(MEM_AREA_IO_SEC, PERIPH_REG_BASE, CORE_MMU_PGDIR_SIZE);
/optee_os/core/arch/arm/plat-marvell/
H A Dmain.c64 register_phys_mem(MEM_AREA_IO_SEC, PLAT_MARVELL_FUSF_FUSE_BASE,
/optee_os/core/arch/riscv/plat-spike/drivers/
H A Dhtif.c17 register_phys_mem(MEM_AREA_IO_NSEC, HTIF_BASE,
/optee_os/core/arch/arm/plat-versal/
H A Dmain.c40 register_phys_mem(MEM_AREA_IO_SEC, PLM_RTCA, PLM_RTCA_LEN);
/optee_os/core/drivers/pm/imx/
H A Dsrc.c30 register_phys_mem(MEM_AREA_IO_SEC, SRC_BASE, SRC_SIZE);
/optee_os/core/arch/arm/plat-ti/
H A Dmain.c30 register_phys_mem(MEM_AREA_RAM_SEC, TZDRAM_BASE, TEE_RAM_VA_SIZE);
/optee_os/core/arch/arm/plat-telechips/drivers/
H A Dtcc_otp.c60 register_phys_mem(MEM_AREA_IO_SEC, OTP_CMD_BASE, OTP_CMD_SIZE);
/optee_os/core/drivers/crypto/caam/hal/common/
H A Dhal_sm.c200 register_phys_mem(MEM_AREA_IO_SEC, SECMEM_BASE, SECMEM_SIZE);
/optee_os/core/drivers/
H A Dimx_sc_api.c88 register_phys_mem(MEM_AREA_IO_SEC, SC_IPC_BASE_SECURE, SC_IPC_SIZE);
/optee_os/core/arch/arm/plat-vexpress/
H A Dmain.c38 register_phys_mem(MEM_AREA_RAM_SEC, TZCDRAM_BASE, TZCDRAM_SIZE);
/optee_os/core/include/mm/
H A Dcore_mmu.h207 #define register_phys_mem(type, addr, size) \ macro
/optee_os/core/drivers/crypto/aspeed/
H A Dhace_ast2600.c40 register_phys_mem(MEM_AREA_IO_SEC, HACE_BASE, SMALL_PAGE_SIZE);
/optee_os/core/arch/arm/plat-sam/
H A Dscmi_server.c19 register_phys_mem(MEM_AREA_IO_NSEC, CFG_SCMI_SHMEM_START, CFG_SCMI_SHMEM_SIZE);
/optee_os/core/arch/arm/plat-stm32mp1/
H A Dscmi_server.c108 register_phys_mem(MEM_AREA_IO_NSEC, CFG_STM32MP1_SCMI_SHM_BASE,
/optee_os/core/mm/
H A Dcore_mmu.c108 register_phys_mem(MEM_AREA_NSEC_SHM, TEE_SHMEM_START, TEE_SHMEM_SIZE);