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Searched refs:cfg (Results 1 – 25 of 65) sorted by relevance

123

/optee_os/core/drivers/
H A Dstpmic1.c709 int stpmic1_bo_enable_cfg(const char *name, struct stpmic1_bo_cfg *cfg) in stpmic1_bo_enable_cfg() argument
713 cfg->ctrl_reg = regul->control_reg; in stpmic1_bo_enable_cfg()
714 cfg->enable_pos = regul->enable_pos; in stpmic1_bo_enable_cfg()
719 int stpmic1_bo_enable_unpg(struct stpmic1_bo_cfg *cfg) in stpmic1_bo_enable_unpg() argument
721 return stpmic1_register_update(cfg->ctrl_reg, in stpmic1_bo_enable_unpg()
722 BIT(cfg->enable_pos), in stpmic1_bo_enable_unpg()
723 BIT(cfg->enable_pos)); in stpmic1_bo_enable_unpg()
728 struct stpmic1_bo_cfg *cfg) in stpmic1_bo_voltage_cfg() argument
741 cfg->ctrl_reg = regul->control_reg; in stpmic1_bo_voltage_cfg()
742 cfg->min_value = min_index << LDO_BUCK_VOLTAGE_SHIFT; in stpmic1_bo_voltage_cfg()
[all …]
H A Dversal_nvm.c257 struct versal_efuse_user_data cfg __aligned_efuse = { in versal_efuse_read_user_data()
273 req.ibuf[0].buf = &cfg; in versal_efuse_read_user_data()
274 req.ibuf[0].len = sizeof(cfg); in versal_efuse_read_user_data()
278 cfg.addr = virt_to_phys((void *)rsp); in versal_efuse_read_user_data()
366 struct versal_efuse_user_data cfg __aligned_efuse = { in versal_efuse_write_user_data()
372 .data.user_fuse_addr = virt_to_phys(&cfg), in versal_efuse_write_user_data()
382 cfg.addr = virt_to_phys(lbuf); in versal_efuse_write_user_data()
386 req.ibuf[1].buf = &cfg; in versal_efuse_write_user_data()
387 req.ibuf[1].len = sizeof(cfg); in versal_efuse_write_user_data()
391 for (i = 0; i < cfg.num; i++) in versal_efuse_write_user_data()
[all …]
H A Dtzc400.c265 void tzc_configure_region(uint8_t region, const struct tzc_region_config *cfg) in tzc_configure_region() argument
267 assert(tzc.base && cfg); in tzc_configure_region()
270 assert(((cfg->filters >> tzc.num_filters) == 0) && in tzc_configure_region()
278 assert(((cfg->top <= (UINT64_MAX >> (64 - tzc.addr_width))) && in tzc_configure_region()
279 (cfg->base < cfg->top))); in tzc_configure_region()
282 assert(((cfg->base | (cfg->top + 1)) & (4096 - 1)) == 0); in tzc_configure_region()
284 assert(cfg->sec_attr <= TZC_REGION_S_RDWR); in tzc_configure_region()
291 tzc_write_region_base_low(tzc.base, region, addr_low(cfg->base)); in tzc_configure_region()
292 tzc_write_region_base_high(tzc.base, region, addr_high(cfg->base)); in tzc_configure_region()
294 tzc_write_region_top_low(tzc.base, region, addr_low(cfg->top)); in tzc_configure_region()
[all …]
H A Datmel_shdwc.c27 #define SHDW_WK_PIN(reg, cfg) ((reg) & \ argument
28 AT91_SHDW_WKUPIS((cfg)->wkup_pin_input))
29 #define SHDW_RTCWK(reg, cfg) (((reg) >> ((cfg)->sr_rtcwk_shift)) & 0x1) argument
30 #define SHDW_RTTWK(reg, cfg) (((reg) >> ((cfg)->sr_rttwk_shift)) & 0x1) argument
31 #define SHDW_RTCWKEN(cfg) BIT((cfg)->mr_rtcwk_shift) argument
32 #define SHDW_RTTWKEN(cfg) BIT((cfg)->mr_rttwk_shift) argument
H A Dversal_puf.c98 struct versal_puf_cfg *cfg) in versal_puf_register() argument
136 req.global_var_filter = cfg->global_var_filter; in versal_puf_register()
137 req.shutter_value = cfg->shutter_value; in versal_puf_register()
138 req.puf_operation = cfg->puf_operation; in versal_puf_register()
139 req.read_option = cfg->read_option; in versal_puf_register()
140 req.reg_mode = cfg->reg_mode; in versal_puf_register()
178 struct versal_puf_cfg *cfg) in versal_puf_regenerate() argument
216 req.global_var_filter = cfg->global_var_filter; in versal_puf_regenerate()
217 req.shutter_value = cfg->shutter_value; in versal_puf_regenerate()
218 req.puf_operation = cfg->puf_operation; in versal_puf_regenerate()
[all …]
H A Dopenedges_omc.c144 void omc_configure_region(uint8_t region, const struct omc_region_config *cfg) in omc_configure_region() argument
152 else if (!cfg) in omc_configure_region()
154 else if (cfg->filters >> tzc.num_filters) in omc_configure_region()
158 else if ((cfg->base | (cfg->top + 1)) & 0xFFF) in omc_configure_region()
162 if (cfg->flags & OMC_FLAG_RELATIVE_ADDR) in omc_configure_region()
167 omc_write_region_base(filter, region, start_addr + cfg->base); in omc_configure_region()
168 omc_write_region_top(filter, region, start_addr + cfg->top); in omc_configure_region()
172 if (cfg->filters & BIT(filter)) in omc_configure_region()
177 cfg->ns_device_access); in omc_configure_region()
H A Dversal_trng.c208 struct trng_cfg cfg; member
513 trng_write32(trng->cfg.addr, off, 0); in trng_write32_range()
522 trng_write32(trng->cfg.addr, off, val); in trng_write32_range()
545 trng_clrset32(trng->cfg.addr, TRNG_CTRL, TRNG_CTRL_PRNGSRST_MASK, in trng_soft_reset()
548 trng_clrset32(trng->cfg.addr, TRNG_CTRL, TRNG_CTRL_PRNGSRST_MASK, 0); in trng_soft_reset()
553 trng_write32(trng->cfg.addr, TRNG_RESET, TRNG_RESET_VAL_MASK); in trng_reset()
555 trng_write32(trng->cfg.addr, TRNG_RESET, 0); in trng_reset()
561 trng_clrset32(trng->cfg.addr, TRNG_CTRL, in trng_hold_reset()
563 trng_write32(trng->cfg.addr, TRNG_RESET, TRNG_RESET_VAL_MASK); in trng_hold_reset()
595 trng_clrset32(trng->cfg.addr, TRNG_CTRL, in trng_collect_random()
[all …]
H A Dstm32_gpio.c149 struct gpio_cfg cfg; member
577 static void get_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) in get_gpio_cfg() argument
591 cfg->mode = (io_read32(bank->base + GPIO_MODER_OFFSET) >> (pin << 1)) & in get_gpio_cfg()
594 cfg->otype = (io_read32(bank->base + GPIO_OTYPER_OFFSET) >> pin) & 1; in get_gpio_cfg()
596 cfg->ospeed = (io_read32(bank->base + GPIO_OSPEEDR_OFFSET) >> in get_gpio_cfg()
599 cfg->pupd = (io_read32(bank->base + GPIO_PUPDR_OFFSET) >> (pin << 1)) & in get_gpio_cfg()
602 cfg->od = (io_read32(bank->base + GPIO_ODR_OFFSET) >> (pin << 1)) & 1; in get_gpio_cfg()
605 cfg->af = (io_read32(bank->base + GPIO_AFRL_OFFSET) >> in get_gpio_cfg()
608 cfg->af = (io_read32(bank->base + GPIO_AFRH_OFFSET) >> in get_gpio_cfg()
616 static void set_gpio_cfg(uint32_t bank_id, uint32_t pin, struct gpio_cfg *cfg) in set_gpio_cfg() argument
[all …]
/optee_os/core/arch/arm/dts/
H A Dstm32mp257f-dk-ca35tdcid-rcc.dtsi120 pll1_cfg_1200Mhz: pll1-cfg-1200Mhz {
121 cfg = <30 1 1 1>;
125 pll1_cfg_1500Mhz: pll1-cfg-1500Mhz {
126 cfg = <75 2 1 1>;
134 pll2_cfg_600Mhz: pll2-cfg-600Mhz {
135 cfg = <30 1 1 2>;
143 pll3_cfg_800Mhz: pll3-cfg-800Mhz {
144 cfg = <20 1 1 1>;
148 pll3_cfg_900Mhz: pll3-cfg-900Mhz {
149 cfg = <45 2 1 1>;
[all …]
H A Dstm32mp257f-ev1-ca35tdcid-rcc.dtsi120 pll1_cfg_1200Mhz: pll1-cfg-1200Mhz {
121 cfg = <30 1 1 1>;
125 pll1_cfg_1500Mhz: pll1-cfg-1500Mhz {
126 cfg = <75 2 1 1>;
134 pll2_cfg_600Mhz: pll2-cfg-600Mhz {
135 cfg = <30 1 1 2>;
143 pll3_cfg_800Mhz: pll3-cfg-800Mhz {
144 cfg = <20 1 1 1>;
148 pll3_cfg_900Mhz: pll3-cfg-900Mhz {
149 cfg = <45 2 1 1>;
[all …]
H A Dstm32mp235f-dk-ca35tdcid-rcc.dtsi113 pll1_cfg_1200Mhz: pll1-cfg-1200Mhz {
114 cfg = <30 1 1 1>;
118 pll1_cfg_1500Mhz: pll1-cfg-1500Mhz {
119 cfg = <75 2 1 1>;
127 pll2_cfg_600Mhz: pll2-cfg-600Mhz {
128 cfg = <30 1 1 2>;
136 pll3_cfg_400Mhz: pll3-cfg-400Mhz {
137 cfg = <20 1 1 2>;
145 pll4_cfg_1200Mhz: pll4-cfg-1200Mhz {
146 cfg = <30 1 1 1>;
[all …]
H A Dstm32mp215f-dk-ca35tdcid-rcc.dtsi113 pll1_cfg_1200MHz: pll1-cfg-1200MHz {
114 cfg = <30 1 1 1>;
118 pll1_cfg_1500MHz: pll1-cfg-1500MHz {
119 cfg = <75 2 1 1>;
127 pll2_cfg_400MHz: pll2-cfg-400MHz {
128 cfg = <20 1 1 2>;
136 pll4_cfg_1200MHz: pll4-cfg-1200MHz {
137 cfg = <30 1 1 1>;
145 pll5_cfg_532MHz: pll5-cfg-532MHz {
146 cfg = <133 5 1 2>;
[all …]
/optee_os/core/include/drivers/
H A Dstpmic1.h221 int stpmic1_bo_enable_cfg(const char *name, struct stpmic1_bo_cfg *cfg);
222 int stpmic1_bo_enable_unpg(struct stpmic1_bo_cfg *cfg);
224 struct stpmic1_bo_cfg *cfg);
225 int stpmic1_bo_voltage_unpg(struct stpmic1_bo_cfg *cfg);
228 struct stpmic1_bo_cfg *cfg);
229 int stpmic1_bo_pull_down_unpg(struct stpmic1_bo_cfg *cfg);
231 int stpmic1_bo_mask_reset_cfg(const char *name, struct stpmic1_bo_cfg *cfg);
232 int stpmic1_bo_mask_reset_unpg(struct stpmic1_bo_cfg *cfg);
235 int stpmic1_lp_cfg(const char *name, struct stpmic1_lp_cfg *cfg);
236 int stpmic1_lp_load_unpg(struct stpmic1_lp_cfg *cfg);
[all …]
/optee_os/core/include/dt-bindings/dma/
H A Dat91.h37 #define AT91_XDMAC_DT_GET_MEM_IF(cfg) \ argument
38 (((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
46 #define AT91_XDMAC_DT_GET_PER_IF(cfg) \ argument
47 (((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
54 #define AT91_XDMAC_DT_GET_PERID(cfg) (((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \ argument
/optee_os/mk/
H A Dconfig.mk167 $(eval $(call cfg-depends-all,CFG_REE_FS_INTEGRITY_RPMB,CFG_RPMB_FS))
234 _CFG_WITH_SECURE_STORAGE := $(call cfg-one-enabled,CFG_REE_FS CFG_RPMB_FS)
364 _CFG_CORE_STACK_PROTECTOR := $(call cfg-one-enabled, CFG_CORE_STACK_PROTECTOR \
367 _CFG_TA_STACK_PROTECTOR := $(call cfg-one-enabled, CFG_TA_STACK_PROTECTOR \
382 $(eval $(call cfg-depends-all,CFG_REE_FS_TA_BUFFERED,CFG_REE_FS_TA))
465 CFG_CORE_BGET_BESTFIT ?= $(call cfg-one-enabled, CFG_WITH_PAGER CFG_LOCKDEP)
545 $(eval $(call cfg-depends-all,CFG_DT_CACHED_NODE_INFO,CFG_EMBED_DTB))
565 _CFG_USE_DTB_OVERLAY := $(call cfg-one-enabled,CFG_EXTERNAL_DTB_OVERLAY \
575 CFG_TRANSFER_LIST_TEST ?= $(call cfg-all-enabled,CFG_TRANSFER_LIST \
639 $(call cfg
[all...]
H A Dcheckconf.mk59 define cfg-vars-by-prefix
72 define cfg-make-define
83 define cfg-cmake-set
92 cfg-one-enabled = $(if $(filter y, $(foreach var,$(1),$($(var)))),y,n)
97 cfg-all-enabled = $(if $(strip $(1)),$(if $(call _cfg-all-enabled,$(1)),y,n),n)
112 cfg-depends-all = \
115 $(if $(filter y,$(call cfg-all-enabled,$(2))), \
127 cfg-depends-one = \
130 $(if $(filter y,$(call cfg-one-enabled,$(2))), \
143 cfg-enable-all-depends = \
[all …]
/optee_os/core/drivers/clk/
H A Dclk-stm32-core.c354 struct clk_stm32_mux_cfg *cfg = clk->priv; in clk_stm32_mux_get_parent() local
356 return stm32_mux_get_parent(cfg->mux_id); in clk_stm32_mux_get_parent()
361 struct clk_stm32_mux_cfg *cfg = clk->priv; in clk_stm32_mux_set_parent() local
363 return stm32_mux_set_parent(cfg->mux_id, pidx); in clk_stm32_mux_set_parent()
374 struct clk_stm32_gate_cfg *cfg = clk->priv; in clk_stm32_gate_enable() local
376 stm32_gate_enable(cfg->gate_id); in clk_stm32_gate_enable()
383 struct clk_stm32_gate_cfg *cfg = clk->priv; in clk_stm32_gate_disable() local
385 stm32_gate_disable(cfg->gate_id); in clk_stm32_gate_disable()
395 struct clk_stm32_gate_cfg *cfg = clk->priv; in clk_stm32_gate_ready_enable() local
397 return stm32_gate_rdy_enable(cfg->gate_id); in clk_stm32_gate_ready_enable()
[all …]
/optee_os/core/arch/arm/plat-stm32mp1/drivers/
H A Dstm32mp1_pmic.c103 struct stpmic1_lp_cfg cfg; member
121 struct regu_lp_config *cfg; member
160 state->cfg = realloc(state->cfg, in dt_get_regu_low_power_config()
161 state->cfg_count * sizeof(*state->cfg)); in dt_get_regu_low_power_config()
162 if (!state->cfg) in dt_get_regu_low_power_config()
165 regu_cfg = &state->cfg[state->cfg_count - 1]; in dt_get_regu_low_power_config()
170 if (stpmic1_lp_cfg(regu_name, &regu_cfg->cfg)) { in dt_get_regu_low_power_config()
200 if (stpmic1_lp_voltage_cfg(regu_name, mv, &regu_cfg->cfg)) { in dt_get_regu_low_power_config()
228 struct stpmic1_lp_cfg *cfg = &state->cfg[i].cfg; in stm32mp_pmic_apply_lp_config() local
230 if ((state->cfg[i].flags & REGU_LP_FLAG_LOAD_PWRCTRL) && in stm32mp_pmic_apply_lp_config()
[all …]
/optee_os/core/drivers/firewall/
H A Dstm32_risaf.c109 #define _RISAF_GET_REGION_ID(cfg) ((cfg) & DT_RISAF_REG_ID_MASK) argument
123 uint32_t cfg; member
209 static uint32_t stm32_risaf_get_region_config(uint32_t cfg) in stm32_risaf_get_region_config() argument
211 return SHIFT_U32((cfg & DT_RISAF_EN_MASK) >> DT_RISAF_EN_SHIFT, in stm32_risaf_get_region_config()
213 SHIFT_U32((cfg & DT_RISAF_SEC_MASK) >> DT_RISAF_SEC_SHIFT, in stm32_risaf_get_region_config()
215 SHIFT_U32((cfg & DT_RISAF_ENC_MASK) >> (DT_RISAF_ENC_SHIFT + 1), in stm32_risaf_get_region_config()
217 SHIFT_U32((cfg & DT_RISAF_PRIV_MASK) >> DT_RISAF_PRIV_SHIFT, in stm32_risaf_get_region_config()
221 static uint32_t stm32_risaf_get_region_cid_config(uint32_t cfg) in stm32_risaf_get_region_cid_config() argument
223 return SHIFT_U32((cfg & DT_RISAF_WRITE_MASK) >> DT_RISAF_WRITE_SHIFT, in stm32_risaf_get_region_cid_config()
225 SHIFT_U32((cfg & DT_RISAF_READ_MASK) >> DT_RISAF_READ_SHIFT, in stm32_risaf_get_region_cid_config()
[all …]
/optee_os/core/
H A Dcrypto.mk102 CFG_CRYPTO_SHA3_ARM_CE ?= $(call cfg-one-enabled, CFG_CRYPTO_SHA3_224 \
159 cryp-enable-all-depends = $(call cfg-enable-all-depends,$(strip $(1)),$(foreach v,$(2),CFG_CRYPTO_$…
165 cryp-dep-one = $(call cfg-depends-one,CFG_CRYPTO_$(strip $(1)),$(patsubst %, CFG_CRYPTO_%,$(strip $…
166 cryp-dep-all = $(call cfg-depends-all,CFG_CRYPTO_$(strip $(1)),$(patsubst %, CFG_CRYPTO_%,$(strip $…
244 _CFG_CORE_LTC_AES := $(call cfg-one-enabled, CFG_CRYPTO_XTS CFG_CRYPTO_CCM \
261 _CFG_CORE_LTC_MD5_DESC := $(call cfg-one-enabled, _CFG_CORE_LTC_MD5_DESC \
263 _CFG_CORE_LTC_SHA1_DESC := $(call cfg-one-enabled, _CFG_CORE_LTC_SHA1_DESC \
265 _CFG_CORE_LTC_SHA224_DESC := $(call cfg-one-enabled, _CFG_CORE_LTC_SHA224_DESC \
267 _CFG_CORE_LTC_SHA256_DESC := $(call cfg-one-enabled, _CFG_CORE_LTC_SHA256_DESC \
270 _CFG_CORE_LTC_SHA384_DESC := $(call cfg-one-enabled, _CFG_CORE_LTC_SHA384_DESC \
[all …]
/optee_os/core/drivers/crypto/caam/
H A Dsub.mk13 subdirs-$(call cfg-one-enabled, CFG_NXP_CAAM_HASH_DRV CFG_NXP_CAAM_HMAC_DRV) += hash
14 subdirs-$(call cfg-one-enabled, CFG_NXP_CAAM_CIPHER_DRV CFG_NXP_CAAM_CMAC_DRV) += cipher
15 subdirs-$(call cfg-one-enabled, CFG_NXP_CAAM_AE_CCM_DRV CFG_NXP_CAAM_AE_GCM_DRV) += ae
/optee_os/core/arch/arm/plat-telechips/
H A Dplat_tzc.c17 struct omc_region_config cfg = { in tzc_protect_teeos() local
25 omc_configure_region(TZC_TEEOS_REGION_NUM, &cfg); in tzc_protect_teeos()
96 struct omc_region_config cfg = { in tzc_configure() local
112 omc_configure_region(0, &cfg); in tzc_configure()
/optee_os/core/arch/arm/plat-sam/
H A Dplatform_sama7g5.c879 struct tzc_region_config cfg = { }; in tzc400_init() local
888 cfg.filters = BIT(0); in tzc400_init()
890 cfg.filters = GENMASK_32(3, 0); in tzc400_init()
891 cfg.sec_attr = TZC_REGION_S_RDWR; in tzc400_init()
893 cfg.base = 0x00000000; in tzc400_init()
894 cfg.top = 0xffffffff; in tzc400_init()
895 cfg.ns_device_access = BIT(16) | BIT(0); in tzc400_init()
896 tzc_configure_region(0, &cfg); in tzc400_init()
898 cfg.base = CFG_TZDRAM_START; in tzc400_init()
899 cfg.top = cfg.base + CFG_TZDRAM_SIZE - 1; in tzc400_init()
[all …]
/optee_os/core/drivers/pinctrl/
H A Datmel_pio.c87 uint32_t cfg = 0; in pio_pinctrl_dt_get() local
124 cfg = func; in pio_pinctrl_dt_get()
137 cfg |= PIO_CFGR_PUEN; in pio_pinctrl_dt_get()
138 cfg &= ~PIO_CFGR_PDEN; in pio_pinctrl_dt_get()
141 cfg |= PIO_CFGR_PDEN; in pio_pinctrl_dt_get()
142 cfg &= ~PIO_CFGR_PUEN; in pio_pinctrl_dt_get()
161 pio_conf->pin_cfg = cfg; in pio_pinctrl_dt_get()
/optee_os/core/lib/scmi-server/
H A Dscmi_server.c80 struct scpfw_config *cfg = scmi_scpfw_get_configuration(); in scmi_server_initialize() local
82 assert(cfg); in scmi_server_initialize()
83 rc = scmi_configure(cfg); in scmi_server_initialize()

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