1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * Copyright (C) 2024 Microchip Technology Inc.
4 */
5
6 #include <assert.h>
7 #include <console.h>
8 #include <drivers/atmel_uart.h>
9 #include <drivers/gic.h>
10 #include <drivers/tzc400.h>
11 #include <io.h>
12 #include <kernel/boot.h>
13 #include <matrix.h>
14 #include <mm/core_mmu.h>
15 #include <platform_config.h>
16 #include <tz_matrix.h>
17 #include <util.h>
18
19 #define MATRIX_SAMA7G54 0
20
21 register_phys_mem_pgdir(MEM_AREA_IO_SEC, CONSOLE_UART_BASE,
22 CORE_MMU_PGDIR_SIZE);
23 register_phys_mem_pgdir(MEM_AREA_IO_SEC, MATRIX_BASE_ADDRESS,
24 CORE_MMU_PGDIR_SIZE);
25 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZC_BASE_ADDRESS, CORE_MMU_PGDIR_SIZE);
26 register_phys_mem_pgdir(MEM_AREA_IO_SEC, TZPM_BASE_ADDRESS,
27 CORE_MMU_PGDIR_SIZE);
28 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_INTERFACE_BASE, GICC_SIZE);
29 register_phys_mem_pgdir(MEM_AREA_IO_SEC, GIC_DISTRIBUTOR_BASE, GICD_SIZE);
30
31 static struct matrix matrixes[] = {
32 {
33 .matrix = MATRIX_SAMA7G54,
34 .p = { .pa = MATRIX_BASE_ADDRESS, },
35 },
36 };
37
38 static struct peri_security peri_security_array[] = {
39 {
40 .peri_id = ID_DWDT_SW,
41 .security_type = SECURITY_TYPE_AS,
42 .addr = DWDT_BASE_ADDRESS,
43 },
44 {
45 .peri_id = ID_DWDT_NSW,
46 .security_type = SECURITY_TYPE_NS,
47 .addr = DWDT_BASE_ADDRESS,
48 },
49 {
50 .peri_id = ID_DWDT_NSW_ALARM,
51 .security_type = SECURITY_TYPE_AS,
52 .addr = DWDT_BASE_ADDRESS,
53 },
54 {
55 .peri_id = ID_SCKC,
56 .security_type = SECURITY_TYPE_AS,
57 .addr = SCKC_BASE_ADDRESS,
58 },
59 {
60 .peri_id = ID_SHDWC,
61 .security_type = SECURITY_TYPE_AS,
62 .addr = SHDWC_BASE_ADDRESS,
63 },
64 {
65 .peri_id = ID_RSTC,
66 .security_type = SECURITY_TYPE_AS,
67 .addr = RSTC_BASE_ADDRESS,
68 },
69 {
70 .peri_id = ID_RTC,
71 .security_type = SECURITY_TYPE_AS,
72 .addr = RTC_BASE_ADDRESS,
73 },
74 {
75 .peri_id = ID_RTT,
76 .security_type = SECURITY_TYPE_AS,
77 .addr = RTT_BASE_ADDRESS,
78 },
79 {
80 .peri_id = ID_CHIPID,
81 .security_type = SECURITY_TYPE_PS,
82 .addr = CHIPID_BASE_ADDRESS,
83 },
84 {
85 .peri_id = ID_PMC,
86 .security_type = SECURITY_TYPE_AS,
87 .addr = PMC_BASE_ADDRESS,
88 },
89 {
90 .peri_id = ID_PIOA,
91 .security_type = SECURITY_TYPE_PS,
92 .addr = PIO_BASE_ADDRESS,
93 },
94 {
95 .peri_id = ID_PIOB,
96 .security_type = SECURITY_TYPE_PS,
97 .addr = PIO_BASE_ADDRESS + 0x40,
98 },
99 {
100 .peri_id = ID_PIOC,
101 .security_type = SECURITY_TYPE_PS,
102 .addr = PIO_BASE_ADDRESS + 0x80,
103 },
104 {
105 .peri_id = ID_PIOD,
106 .security_type = SECURITY_TYPE_PS,
107 .addr = PIO_BASE_ADDRESS + 0xC0,
108 },
109 {
110 .peri_id = ID_PIOE,
111 .security_type = SECURITY_TYPE_PS,
112 .addr = PIO_BASE_ADDRESS + 0x100,
113 },
114 {
115 .peri_id = ID_SECUMOD,
116 .security_type = SECURITY_TYPE_AS,
117 .addr = SECUMOD_BASE_ADDRESS,
118 },
119 {
120 .peri_id = ID_SECURAM,
121 .security_type = SECURITY_TYPE_AS,
122 .addr = 0xE0000000,
123 },
124 {
125 .peri_id = ID_SFR,
126 .security_type = SECURITY_TYPE_PS,
127 .addr = SFR_BASE_ADDRESS,
128 },
129 {
130 .peri_id = ID_SFRBU,
131 .security_type = SECURITY_TYPE_AS,
132 .addr = SFRBU_BASE_ADDRESS,
133 },
134 {
135 .peri_id = ID_HSMC,
136 .security_type = SECURITY_TYPE_PS,
137 .addr = HSMC_BASE_ADDRESS,
138 },
139 {
140 .peri_id = ID_XDMAC0,
141 .security_type = SECURITY_TYPE_PS,
142 .addr = XDMAC0_BASE_ADDRESS,
143 },
144 {
145 .peri_id = ID_XDMAC1,
146 .security_type = SECURITY_TYPE_PS,
147 .addr = XDMAC1_BASE_ADDRESS,
148 },
149 {
150 .peri_id = ID_XDMAC2,
151 .security_type = SECURITY_TYPE_PS,
152 .addr = XDMAC2_BASE_ADDRESS,
153 },
154 {
155 .peri_id = ID_ACC,
156 .security_type = SECURITY_TYPE_PS,
157 .addr = ACC_BASE_ADDRESS,
158 },
159 {
160 .peri_id = ID_ADC,
161 .security_type = SECURITY_TYPE_PS,
162 .addr = ADC_BASE_ADDRESS,
163 },
164 {
165 .peri_id = ID_AES,
166 .security_type = SECURITY_TYPE_PS,
167 .addr = AES_BASE_ADDRESS,
168 },
169 {
170 .peri_id = ID_TZAESBASC,
171 .security_type = SECURITY_TYPE_AS,
172 .addr = TZAESBASC_BASE_ADDRESS,
173 },
174 {
175 .peri_id = ID_ASRC,
176 .security_type = SECURITY_TYPE_PS,
177 .addr = ASRC_BASE_ADDRESS,
178 },
179 {
180 .peri_id = ID_CPKCC,
181 .security_type = SECURITY_TYPE_PS,
182 .addr = CPKCC_BASE_ADDRESS,
183 },
184 {
185 .peri_id = ID_CSI,
186 .security_type = SECURITY_TYPE_PS,
187 .addr = CSI_BASE_ADDRESS,
188 },
189 {
190 .peri_id = ID_CSI2DC,
191 .security_type = SECURITY_TYPE_PS,
192 .addr = CSI2DC_BASE_ADDRESS,
193 },
194 {
195 .peri_id = ID_DDRPUBL,
196 .security_type = SECURITY_TYPE_PS,
197 .addr = DDRPUBL_BASE_ADDRESS,
198 },
199 {
200 .peri_id = ID_DDRUMCTL,
201 .security_type = SECURITY_TYPE_PS,
202 .addr = DDRUMCTL_BASE_ADDRESS,
203 },
204 {
205 .peri_id = ID_EIC,
206 .security_type = SECURITY_TYPE_PS,
207 .addr = EIC_BASE_ADDRESS,
208 },
209 {
210 .peri_id = ID_FLEXCOM0,
211 .security_type = SECURITY_TYPE_PS,
212 .addr = FLEXCOM0_BASE_ADDRESS,
213 },
214 {
215 .peri_id = ID_FLEXCOM1,
216 .security_type = SECURITY_TYPE_PS,
217 .addr = FLEXCOM1_BASE_ADDRESS,
218 },
219 {
220 .peri_id = ID_FLEXCOM2,
221 .security_type = SECURITY_TYPE_PS,
222 .addr = FLEXCOM2_BASE_ADDRESS,
223 },
224 {
225 .peri_id = ID_FLEXCOM3,
226 .security_type = SECURITY_TYPE_PS,
227 .addr = FLEXCOM3_BASE_ADDRESS,
228 },
229 {
230 .peri_id = ID_FLEXCOM4,
231 .security_type = SECURITY_TYPE_PS,
232 .addr = FLEXCOM4_BASE_ADDRESS,
233 },
234 {
235 .peri_id = ID_FLEXCOM5,
236 .security_type = SECURITY_TYPE_PS,
237 .addr = FLEXCOM5_BASE_ADDRESS,
238 },
239 {
240 .peri_id = ID_FLEXCOM6,
241 .security_type = SECURITY_TYPE_PS,
242 .addr = FLEXCOM6_BASE_ADDRESS,
243 },
244 {
245 .peri_id = ID_FLEXCOM7,
246 .security_type = SECURITY_TYPE_PS,
247 .addr = FLEXCOM7_BASE_ADDRESS,
248 },
249 {
250 .peri_id = ID_FLEXCOM8,
251 .security_type = SECURITY_TYPE_PS,
252 .addr = FLEXCOM8_BASE_ADDRESS,
253 },
254 {
255 .peri_id = ID_FLEXCOM9,
256 .security_type = SECURITY_TYPE_PS,
257 .addr = FLEXCOM9_BASE_ADDRESS,
258 },
259 {
260 .peri_id = ID_FLEXCOM10,
261 .security_type = SECURITY_TYPE_PS,
262 .addr = FLEXCOM10_BASE_ADDRESS,
263 },
264 {
265 .peri_id = ID_FLEXCOM11,
266 .security_type = SECURITY_TYPE_PS,
267 .addr = FLEXCOM11_BASE_ADDRESS,
268 },
269 {
270 .peri_id = ID_GMAC0,
271 .security_type = SECURITY_TYPE_PS,
272 .addr = GMAC0_BASE_ADDRESS,
273 },
274 {
275 .peri_id = ID_GMAC1,
276 .security_type = SECURITY_TYPE_PS,
277 .addr = GMAC1_BASE_ADDRESS,
278 },
279 {
280 .peri_id = ID_GMAC0_TSU,
281 .security_type = SECURITY_TYPE_PS,
282 },
283 {
284 .peri_id = ID_GMAC1_TSU,
285 .security_type = SECURITY_TYPE_PS,
286 },
287 {
288 .peri_id = ID_ICM,
289 .security_type = SECURITY_TYPE_AS,
290 .addr = ICM_BASE_ADDRESS,
291 },
292 {
293 .peri_id = ID_ISC,
294 .security_type = SECURITY_TYPE_PS,
295 .addr = ISC_BASE_ADDRESS,
296 },
297 {
298 .peri_id = ID_I2SMCC0,
299 .security_type = SECURITY_TYPE_PS,
300 .addr = I2SMCC0_BASE_ADDRESS,
301 },
302 {
303 .peri_id = ID_I2SMCC1,
304 .security_type = SECURITY_TYPE_PS,
305 .addr = I2SMCC1_BASE_ADDRESS,
306 },
307 {
308 .peri_id = ID_MATRIX,
309 .security_type = SECURITY_TYPE_AS,
310 .addr = MATRIX_BASE_ADDRESS,
311 },
312 {
313 .peri_id = ID_MCAN0,
314 .security_type = SECURITY_TYPE_PS,
315 .addr = MCAN0_BASE_ADDRESS,
316 },
317 {
318 .peri_id = ID_MCAN1,
319 .security_type = SECURITY_TYPE_PS,
320 .addr = MCAN1_BASE_ADDRESS,
321 },
322 {
323 .peri_id = ID_MCAN2,
324 .security_type = SECURITY_TYPE_PS,
325 .addr = MCAN2_BASE_ADDRESS,
326 },
327 {
328 .peri_id = ID_MCAN3,
329 .security_type = SECURITY_TYPE_PS,
330 .addr = MCAN3_BASE_ADDRESS,
331 },
332 {
333 .peri_id = ID_MCAN4,
334 .security_type = SECURITY_TYPE_PS,
335 .addr = MCAN4_BASE_ADDRESS,
336 },
337 {
338 .peri_id = ID_MCAN5,
339 .security_type = SECURITY_TYPE_PS,
340 .addr = MCAN5_BASE_ADDRESS,
341 },
342 {
343 .peri_id = ID_OTPC,
344 .security_type = SECURITY_TYPE_PS,
345 .addr = OTPC_BASE_ADDRESS,
346 },
347 {
348 .peri_id = ID_PDMC0,
349 .security_type = SECURITY_TYPE_PS,
350 .addr = PDMC0_BASE_ADDRESS,
351 },
352 {
353 .peri_id = ID_PDMC1,
354 .security_type = SECURITY_TYPE_PS,
355 .addr = PDMC1_BASE_ADDRESS,
356 },
357 {
358 .peri_id = ID_PIT64B0,
359 .security_type = SECURITY_TYPE_PS,
360 .addr = PIT64B0_BASE_ADDRESS,
361 },
362 {
363 .peri_id = ID_PIT64B1,
364 .security_type = SECURITY_TYPE_PS,
365 .addr = PIT64B1_BASE_ADDRESS,
366 },
367 {
368 .peri_id = ID_PIT64B2,
369 .security_type = SECURITY_TYPE_PS,
370 .addr = PIT64B2_BASE_ADDRESS,
371 },
372 {
373 .peri_id = ID_PIT64B3,
374 .security_type = SECURITY_TYPE_PS,
375 .addr = PIT64B3_BASE_ADDRESS,
376 },
377 {
378 .peri_id = ID_PIT64B4,
379 .security_type = SECURITY_TYPE_PS,
380 .addr = PIT64B4_BASE_ADDRESS,
381 },
382 {
383 .peri_id = ID_PIT64B5,
384 .security_type = SECURITY_TYPE_PS,
385 .addr = PIT64B5_BASE_ADDRESS,
386 },
387 {
388 .peri_id = ID_PWM,
389 .security_type = SECURITY_TYPE_PS,
390 .addr = PWM_BASE_ADDRESS,
391 },
392 {
393 .peri_id = ID_QSPI0,
394 .security_type = SECURITY_TYPE_PS,
395 .addr = QSPI0_BASE_ADDRESS,
396 },
397 {
398 .peri_id = ID_QSPI1,
399 .security_type = SECURITY_TYPE_PS,
400 .addr = QSPI1_BASE_ADDRESS,
401 },
402 {
403 .peri_id = ID_SDMMC0,
404 .security_type = SECURITY_TYPE_PS,
405 .addr = SDMMC0_BASE_ADDRESS,
406 },
407 {
408 .peri_id = ID_SDMMC1,
409 .security_type = SECURITY_TYPE_PS,
410 .addr = SDMMC1_BASE_ADDRESS,
411 },
412 {
413 .peri_id = ID_SDMMC2,
414 .security_type = SECURITY_TYPE_PS,
415 .addr = SDMMC2_BASE_ADDRESS,
416 },
417 {
418 .peri_id = ID_SHA,
419 .security_type = SECURITY_TYPE_PS,
420 .addr = SHA_BASE_ADDRESS,
421 },
422 {
423 .peri_id = ID_SPDIFRX,
424 .security_type = SECURITY_TYPE_PS,
425 .addr = SPDIFRX_BASE_ADDRESS,
426 },
427 {
428 .peri_id = ID_SPDIFTX,
429 .security_type = SECURITY_TYPE_PS,
430 .addr = SPDIFTX_BASE_ADDRESS,
431 },
432 {
433 .peri_id = ID_SSC0,
434 .security_type = SECURITY_TYPE_PS,
435 .addr = SSC0_BASE_ADDRESS,
436 },
437 {
438 .peri_id = ID_SSC1,
439 .security_type = SECURITY_TYPE_PS,
440 .addr = SSC1_BASE_ADDRESS,
441 },
442 {
443 .peri_id = ID_TC0_CHANNEL0,
444 .security_type = SECURITY_TYPE_PS,
445 .addr = TC0_BASE_ADDRESS,
446 },
447 {
448 .peri_id = ID_TC0_CHANNEL1,
449 .security_type = SECURITY_TYPE_PS,
450 .addr = TC0_BASE_ADDRESS + 0x40,
451 },
452 {
453 .peri_id = ID_TC0_CHANNEL2,
454 .security_type = SECURITY_TYPE_PS,
455 .addr = TC0_BASE_ADDRESS + 0x80,
456 },
457 {
458 .peri_id = ID_TC1_CHANNEL0,
459 .security_type = SECURITY_TYPE_PS,
460 .addr = TC1_BASE_ADDRESS,
461 },
462 {
463 .peri_id = ID_TC1_CHANNEL1,
464 .security_type = SECURITY_TYPE_PS,
465 .addr = TC1_BASE_ADDRESS + 0x40,
466 },
467 {
468 .peri_id = ID_TC1_CHANNEL2,
469 .security_type = SECURITY_TYPE_PS,
470 .addr = TC1_BASE_ADDRESS + 0x80,
471 },
472 {
473 .peri_id = ID_TCPCA,
474 .security_type = SECURITY_TYPE_PS,
475 .addr = TCPCA_BASE_ADDRESS,
476 },
477 {
478 .peri_id = ID_TCPCB,
479 .security_type = SECURITY_TYPE_PS,
480 .addr = TCPCB_BASE_ADDRESS,
481 },
482 {
483 .peri_id = ID_TDES,
484 .security_type = SECURITY_TYPE_PS,
485 .addr = TDES_BASE_ADDRESS,
486 },
487 {
488 .peri_id = ID_TRNG,
489 .security_type = SECURITY_TYPE_PS,
490 .addr = TRNG_BASE_ADDRESS,
491 },
492 {
493 .peri_id = ID_TZAESB_NS,
494 .security_type = SECURITY_TYPE_PS,
495 .addr = TZAESBNS_BASE_ADDRESS,
496 },
497 {
498 .peri_id = ID_TZAESB_NS_SINT,
499 .security_type = SECURITY_TYPE_AS,
500 .addr = TZAESBNS_BASE_ADDRESS,},
501 {
502 .peri_id = ID_TZAESB_S,
503 .security_type = SECURITY_TYPE_PS,
504 .addr = TZAESBS_BASE_ADDRESS,
505 },
506 {
507 .peri_id = ID_TZAESB_S_SINT,
508 .security_type = SECURITY_TYPE_AS,
509 .addr = TZAESBS_BASE_ADDRESS,
510 },
511 {
512 .peri_id = ID_TZC,
513 .security_type = SECURITY_TYPE_AS,
514 .addr = TZC_BASE_ADDRESS,
515 },
516 {
517 .peri_id = ID_TZPM,
518 .security_type = SECURITY_TYPE_PS,
519 .addr = TZPM_BASE_ADDRESS,
520 },
521 {
522 .peri_id = ID_UDPHSA,
523 .security_type = SECURITY_TYPE_PS,
524 .addr = UDPHSA_BASE_ADDRESS,
525 },
526 {
527 .peri_id = ID_UDPHSB,
528 .security_type = SECURITY_TYPE_PS,
529 .addr = UDPHSB_BASE_ADDRESS,
530 },
531 {
532 .peri_id = ID_UHPHS,
533 .security_type = SECURITY_TYPE_PS,
534 },
535 {
536 .peri_id = ID_XDMAC0_SINT,
537 .security_type = SECURITY_TYPE_PS,
538 .addr = XDMAC0_BASE_ADDRESS,
539 },
540 {
541 .peri_id = ID_XDMAC1_SINT,
542 .security_type = SECURITY_TYPE_PS,
543 .addr = XDMAC1_BASE_ADDRESS,
544 },
545 {
546 .peri_id = ID_XDMAC2_SINT,
547 .security_type = SECURITY_TYPE_PS,
548 .addr = XDMAC2_BASE_ADDRESS,
549 },
550 {
551 .peri_id = ID_AES_SINT,
552 .security_type = SECURITY_TYPE_PS,
553 .addr = AES_BASE_ADDRESS,
554 },
555 {
556 .peri_id = ID_GMAC0_Q1,
557 .security_type = SECURITY_TYPE_PS,
558 },
559 {
560 .peri_id = ID_GMAC0_Q2,
561 .security_type = SECURITY_TYPE_PS,
562 },
563 {
564 .peri_id = ID_GMAC0_Q3,
565 .security_type = SECURITY_TYPE_PS,
566 },
567 {
568 .peri_id = ID_GMAC0_Q4,
569 .security_type = SECURITY_TYPE_PS,
570 },
571 {
572 .peri_id = ID_GMAC0_Q5,
573 .security_type = SECURITY_TYPE_PS,
574 },
575 {
576 .peri_id = ID_GMAC1_Q1,
577 .security_type = SECURITY_TYPE_PS,
578 },
579 {
580 .peri_id = ID_ICM_SINT,
581 .security_type = SECURITY_TYPE_AS,
582 .addr = ICM_BASE_ADDRESS,
583 },
584 {
585 .peri_id = ID_MCAN0_INT1,
586 .security_type = SECURITY_TYPE_PS,
587 .addr = MCAN0_BASE_ADDRESS,
588 },
589 {
590 .peri_id = ID_MCAN1_INT1,
591 .security_type = SECURITY_TYPE_PS,
592 .addr = MCAN1_BASE_ADDRESS,
593 },
594 {
595 .peri_id = ID_MCAN2_INT1,
596 .security_type = SECURITY_TYPE_PS,
597 .addr = MCAN2_BASE_ADDRESS,
598 },
599 {
600 .peri_id = ID_MCAN3_INT1,
601 .security_type = SECURITY_TYPE_PS,
602 .addr = MCAN3_BASE_ADDRESS,
603 },
604 {
605 .peri_id = ID_MCAN4_INT1,
606 .security_type = SECURITY_TYPE_PS,
607 .addr = MCAN4_BASE_ADDRESS,
608 },
609 {
610 .peri_id = ID_MCAN5_INT1,
611 .security_type = SECURITY_TYPE_PS,
612 .addr = MCAN5_BASE_ADDRESS,
613 },
614 {
615 .peri_id = ID_PIOA_SINT,
616 .security_type = SECURITY_TYPE_PS,
617 .addr = PIO_BASE_ADDRESS,
618 },
619 {
620 .peri_id = ID_PIOB_SINT,
621 .security_type = SECURITY_TYPE_PS,
622 .addr = PIO_BASE_ADDRESS + 0x40,
623 },
624 {
625 .peri_id = ID_PIOC_SINT,
626 .security_type = SECURITY_TYPE_PS,
627 .addr = PIO_BASE_ADDRESS + 0x80,
628 },
629 {
630 .peri_id = ID_PIOD_SINT,
631 .security_type = SECURITY_TYPE_PS,
632 .addr = PIO_BASE_ADDRESS + 0xC0,
633 },
634 {
635 .peri_id = ID_PIOE_SINT,
636 .security_type = SECURITY_TYPE_PS,
637 .addr = PIO_BASE_ADDRESS + 0x100,
638 },
639 {
640 .peri_id = ID_PIT64B0_SINT,
641 .security_type = SECURITY_TYPE_PS,
642 .addr = PIT64B0_BASE_ADDRESS,
643 },
644 {
645 .peri_id = ID_PIT64B1_SINT,
646 .security_type = SECURITY_TYPE_PS,
647 .addr = PIT64B1_BASE_ADDRESS,
648 },
649 {
650 .peri_id = ID_PIT64B2_SINT,
651 .security_type = SECURITY_TYPE_PS,
652 .addr = PIT64B2_BASE_ADDRESS,
653 },
654 {
655 .peri_id = ID_PIT64B3_SINT,
656 .security_type = SECURITY_TYPE_PS,
657 .addr = PIT64B3_BASE_ADDRESS,
658 },
659 {
660 .peri_id = ID_PIT64B4_SINT,
661 .security_type = SECURITY_TYPE_PS,
662 .addr = PIT64B4_BASE_ADDRESS,
663 },
664 {
665 .peri_id = ID_PIT64B5_SINT,
666 .security_type = SECURITY_TYPE_PS,
667 .addr = PIT64B5_BASE_ADDRESS,
668 },
669 {
670 .peri_id = ID_SDMMC0_TIMER,
671 .security_type = SECURITY_TYPE_PS,
672 },
673 {
674 .peri_id = ID_SDMMC1_TIMER,
675 .security_type = SECURITY_TYPE_PS,
676 },
677 {
678 .peri_id = ID_SDMMC2_TIMER,
679 .security_type = SECURITY_TYPE_PS,
680 },
681 {
682 .peri_id = ID_SHA_SINT,
683 .security_type = SECURITY_TYPE_PS,
684 .addr = SHA_BASE_ADDRESS,
685 },
686 {
687 .peri_id = ID_TC0_SINT0,
688 .security_type = SECURITY_TYPE_PS,
689 .addr = TC0_BASE_ADDRESS,
690 },
691 {
692 .peri_id = ID_TC0_SINT1,
693 .security_type = SECURITY_TYPE_PS,
694 .addr = TC0_BASE_ADDRESS,
695 },
696 {
697 .peri_id = ID_TC0_SINT2,
698 .security_type = SECURITY_TYPE_PS,
699 .addr = TC0_BASE_ADDRESS,
700 },
701 {
702 .peri_id = ID_TC1_SINT0,
703 .security_type = SECURITY_TYPE_PS,
704 .addr = TC1_BASE_ADDRESS,
705 },
706 {
707 .peri_id = ID_TC1_SINT1,
708 .security_type = SECURITY_TYPE_PS,
709 .addr = TC1_BASE_ADDRESS,
710 },
711 {
712 .peri_id = ID_TC1_SINT2,
713 .security_type = SECURITY_TYPE_PS,
714 .addr = TC1_BASE_ADDRESS,
715 },
716 {
717 .peri_id = ID_TDES_SINT,
718 .security_type = SECURITY_TYPE_PS,
719 .addr = TDES_BASE_ADDRESS,
720 },
721 {
722 .peri_id = ID_TRNG_SINT,
723 .security_type = SECURITY_TYPE_PS,
724 .addr = TRNG_BASE_ADDRESS,
725 },
726 {
727 .peri_id = ID_EXT_IRQ0,
728 .security_type = SECURITY_TYPE_PS,
729 },
730 {
731 .peri_id = ID_EXT_IRQ1,
732 .security_type = SECURITY_TYPE_PS,
733 },
734 };
735
736 static struct atmel_uart_data console_data;
737
plat_console_init(void)738 void plat_console_init(void)
739 {
740 atmel_uart_init(&console_data, CONSOLE_UART_BASE);
741 register_serial_console(&console_data.chip);
742 }
743
peri_security_get(unsigned int idx)744 struct peri_security *peri_security_get(unsigned int idx)
745 {
746 struct peri_security *p = NULL;
747
748 if (idx < ARRAY_SIZE(peri_security_array))
749 p = &peri_security_array[idx];
750
751 return p;
752 }
753
matrix_get(unsigned int idx)754 struct matrix *matrix_get(unsigned int idx)
755 {
756 struct matrix *p = NULL;
757
758 if (idx < ARRAY_SIZE(matrixes))
759 p = &matrixes[idx];
760
761 return p;
762 }
763
matrix_configure_slave(void)764 static void matrix_configure_slave(void)
765 {
766 unsigned int sasplit_setting = 0;
767 unsigned int srtop_setting = 0;
768 unsigned int ssr_setting = 0;
769 unsigned int base = 0;
770
771 static_assert(CFG_TZDRAM_START == DDR_CS_ADDR);
772 static_assert(CFG_TZDRAM_SIZE == 0x800000);
773
774 base = matrix_base(MATRIX_SAMA7G54);
775
776 /* 0: QSPI0: Normal world */
777 /* 1: QSPI1: Normal world */
778 srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_128M) |
779 MATRIX_SRTOP(1, MATRIX_SRTOP_VALUE_128M);
780 sasplit_setting = MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_128M) |
781 MATRIX_SASPLIT(1, MATRIX_SASPLIT_VALUE_128M);
782 ssr_setting = MATRIX_LANSECH_NS(0) |
783 MATRIX_LANSECH_NS(1) |
784 MATRIX_RDNSECH_NS(0) |
785 MATRIX_RDNSECH_NS(1) |
786 MATRIX_WRNSECH_NS(0) |
787 MATRIX_WRNSECH_NS(1);
788 matrix_configure_slave_security(base, 0, srtop_setting,
789 sasplit_setting, ssr_setting);
790 matrix_configure_slave_security(base, 1, srtop_setting,
791 sasplit_setting, ssr_setting);
792
793 /* 2: TZAESB: Default */
794
795 /* 3: UDDRC_P1: Non-Secure, except op-tee tee/ta memory */
796 /*
797 * Matrix DDR configuration is hardcoded here and is difficult to
798 * generate at runtime. Since this configuration expect the secure
799 * DRAM to be at start of RAM and 8M of size, enforce it here.
800 */
801 srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_128M);
802 sasplit_setting = MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_8M);
803 ssr_setting = MATRIX_LANSECH_S(0) |
804 MATRIX_RDNSECH_S(0) |
805 MATRIX_WRNSECH_S(0);
806 matrix_configure_slave_security(base, 3, srtop_setting,
807 sasplit_setting, ssr_setting);
808
809 /* 4: APB6: Default */
810
811 /*
812 * 5: SRAM_P0
813 * 6: SRAM_P1
814 */
815 srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_128K);
816 sasplit_setting = MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_64K);
817 ssr_setting = MATRIX_LANSECH_NS(0) |
818 MATRIX_RDNSECH_S(0) |
819 MATRIX_WRNSECH_S(0);
820 matrix_configure_slave_security(base, 5, srtop_setting,
821 sasplit_setting, ssr_setting);
822 matrix_configure_slave_security(base, 6, srtop_setting,
823 sasplit_setting, ssr_setting);
824
825 /*
826 * 7: SMC
827 * EBI_CS0 ----> Slave Region 0
828 * EBI_CS1 ----> Slave Region 1
829 * EBI_CS2 ----> Slave Region 2
830 * EBI_CS3 ----> Slave Region 3
831 * NFC_CMD ----> Slave Region 4 : Non-Secure
832 */
833 srtop_setting = MATRIX_SRTOP(4, MATRIX_SRTOP_VALUE_128M);
834 sasplit_setting = MATRIX_SASPLIT(4, MATRIX_SASPLIT_VALUE_128M);
835 ssr_setting = MATRIX_LANSECH_NS(4) |
836 MATRIX_RDNSECH_NS(4) |
837 MATRIX_WRNSECH_NS(4);
838 matrix_configure_slave_security(base, 7, srtop_setting,
839 sasplit_setting, ssr_setting);
840
841 /*
842 * 8: NFC_RAM
843 * Slave area below SASSPLIT boundary is configured as Not Secured
844 */
845 srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_8K);
846 sasplit_setting = MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_8K);
847 ssr_setting = MATRIX_LANSECH_NS(0);
848 matrix_configure_slave_security(base, 8, srtop_setting,
849 sasplit_setting, ssr_setting);
850
851 /*
852 * 9: USB_RAM
853 * Slave area below SASSPLIT boundary is configured as Not Secured
854 */
855 srtop_setting = MATRIX_SRTOP(0, MATRIX_SRTOP_VALUE_1M) |
856 MATRIX_SRTOP(1, MATRIX_SRTOP_VALUE_1M) |
857 MATRIX_SRTOP(2, MATRIX_SRTOP_VALUE_4K) |
858 MATRIX_SRTOP(3, MATRIX_SRTOP_VALUE_4K);
859 sasplit_setting = MATRIX_SASPLIT(0, MATRIX_SASPLIT_VALUE_1M) |
860 MATRIX_SASPLIT(1, MATRIX_SASPLIT_VALUE_1M) |
861 MATRIX_SASPLIT(2, MATRIX_SASPLIT_VALUE_4K) |
862 MATRIX_SASPLIT(3, MATRIX_SASPLIT_VALUE_4K);
863 ssr_setting = MATRIX_LANSECH_NS(0) |
864 MATRIX_LANSECH_NS(1) |
865 MATRIX_LANSECH_NS(2) |
866 MATRIX_LANSECH_NS(3);
867 matrix_configure_slave_security(base, 9, srtop_setting,
868 sasplit_setting, ssr_setting);
869 }
870
matrix_init(void)871 static void matrix_init(void)
872 {
873 matrix_write_protect_disable(matrix_base(MATRIX_SAMA7G54));
874 matrix_configure_slave();
875 }
876
tzc400_init(void)877 static void tzc400_init(void)
878 {
879 struct tzc_region_config cfg = { };
880 unsigned int tzc_idx = 0;
881 vaddr_t addr = 0;
882
883 for (tzc_idx = 0; tzc_idx <= 1; tzc_idx++) {
884 addr = TZC_BASE_ADDRESS + 0x1000 * tzc_idx;
885 tzc_init(addr);
886
887 if (tzc_idx)
888 cfg.filters = BIT(0);
889 else
890 cfg.filters = GENMASK_32(3, 0);
891 cfg.sec_attr = TZC_REGION_S_RDWR;
892
893 cfg.base = 0x00000000;
894 cfg.top = 0xffffffff;
895 cfg.ns_device_access = BIT(16) | BIT(0);
896 tzc_configure_region(0, &cfg);
897
898 cfg.base = CFG_TZDRAM_START;
899 cfg.top = cfg.base + CFG_TZDRAM_SIZE - 1;
900 cfg.ns_device_access = 0;
901 tzc_configure_region(1, &cfg);
902
903 cfg.base += CFG_TZDRAM_SIZE;
904 cfg.top = cfg.base - CFG_TZDRAM_SIZE + DDR_CS_SIZE - 1;
905 cfg.ns_device_access = BIT(16) | BIT(0);
906 tzc_configure_region(2, &cfg);
907 }
908 }
909
tzpm_init(void)910 static void tzpm_init(void)
911 {
912 struct peri_security *p = peri_security_array;
913 unsigned int i = 0;
914 vaddr_t addr = TZPM_BASE_ADDRESS;
915
916 /* TZPM_PIDx register write is possible. */
917 io_write32(addr + 0x04, 0x12AC4B5D);
918
919 for (i = 0; i < ARRAY_SIZE(peri_security_array); i++, p++)
920 if (p->peri_id < 128 &&
921 p->security_type == SECURITY_TYPE_PS)
922 io_setbits32(addr + 8 + 4 * (p->peri_id / 32),
923 BIT(p->peri_id % 32));
924 }
925
plat_primary_init_early(void)926 void plat_primary_init_early(void)
927 {
928 assert(!cpu_mmu_enabled());
929 matrix_init();
930 tzc400_init();
931 tzpm_init();
932 }
933
boot_primary_init_intc(void)934 void boot_primary_init_intc(void)
935 {
936 gic_init(GIC_INTERFACE_BASE, GIC_DISTRIBUTOR_BASE);
937 }
938