| /optee_os/core/include/drivers/ |
| H A D | zynqmp_pm.h | 29 #define ZYNQMP_EFUSE_LEN(_id) ZYNQMP_EFUSE_##_id##_LENGTH argument
32 #define ZYNQMP_EFUSE_MEM(_id) (ROUNDUP(ZYNQMP_EFUSE_LEN(_id), CACHELINE_LEN)) argument
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| /optee_os/core/drivers/crypto/crypto_api/include/ |
| H A D | drvcrypt_asn1_oid.h | 129 #define DRVCRYPT_OID_LEN(_id) (sizeof(_id) - 1) argument
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| /optee_os/ta/pkcs11/src/ |
| H A D | pkcs11_helpers.c | 28 #define PKCS11_ID_SZ(_id, _sz) \ argument
29 { .id = (uint32_t)(_id), .size = (_sz), .string = #_id }
31 #define PKCS11_ID_SZ(_id, _sz) \ argument
32 { .id = (uint32_t)(_id), .size = (_sz) }
116 #define PKCS11_ID(_id) { .id = _id, .string = #_id } argument
118 #define PKCS11_ID(_id) { .id = _id } argument
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| /optee_os/core/arch/arm/plat-stm32mp1/drivers/ |
| H A D | stm32mp1_pwr.c | 161 #define DEFINE_REG(_id, _name, _supply) { \ argument
165 .priv = (void *)(pwr_regulators + (_id)), \
166 .regulator = pwr_regu_device + (_id), \
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| /optee_os/core/arch/arm/plat-stm32mp1/ |
| H A D | scmi_server.c | 121 #define CLOCK_CELL(_scmi_id, _id, _name, _init_enabled) \ argument
123 .clock_id = (_id), \
130 #define CLOCK_CELL_DECPROT(_scmi_id, _id, _name, _init_enabled, _etzpc_id) \ argument
132 .clock_id = (_id), \
139 #define RESET_CELL(_scmi_id, _id, _name) \ argument
141 .reset_id = (_id), \
147 #define RESET_CELL_DECPROT(_scmi_id, _id, _name, _etzpc_id) \ argument
149 .reset_id = (_id), \
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| /optee_os/core/drivers/regulator/ |
| H A D | stm32mp13_regulator_iod.c | 254 #define DEFINE_REG(_id, _name, _supply_name) { \ argument
257 .priv = iod_regulator_priv + (_id), \
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| /optee_os/core/drivers/clk/sam/ |
| H A D | at91_pmc.h | 152 #define AT91_PMC_MCR_V2_ID(_id) ((_id) & AT91_PMC_MCR_V2_ID_MASK) argument
|
| H A D | clk-sam9x60-pll.c | 60 #define WAIT_PLL_READY_TIMEOUT(_base, _id) \ argument
67 BIT(_id); \
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| /optee_os/core/drivers/ |
| H A D | versal_puf.c | 20 #define PUF_API_ID(_id) ((VERSAL_PUF_MODULE << VERSAL_PUF_MODULE_SHIFT) | (_id)) argument
|
| H A D | stm32_tamp.c | 136 typeof(id) _id = (id); \
137 GENMASK_32(((_id) - EXT_TAMP1 + 1) * 2 + 7, \
138 ((_id) - EXT_TAMP1) * 2 + 8); \
147 typeof(id) _id = (id); \
148 GENMASK_32(((_id) - EXT_TAMP1 + 1) * 3 + 7, \
149 ((_id) - EXT_TAMP1) * 3 + 8); \
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| H A D | versal_nvm.c | 24 #define NVM_API_ID(_id) ((NVM_MODULE << NVM_MODULE_SHIFT) | (_id)) argument
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| /optee_os/core/drivers/clk/ |
| H A D | clk-stm32mp13.c | 270 #define GATE_CFG(_id, _offset, _bit_idx, _offset_clr)\ argument
271 [(_id)] = {\
444 #define MUXRDY_CFG(_id, _offset, _shift, _witdh, _rdy)\ argument
445 [(_id)] = {\
452 #define MUX_CFG(_id, _offset, _shift, _witdh)\ argument
453 MUXRDY_CFG(_id, _offset, _shift, _witdh, MUX_NO_RDY)
527 #define DIVRDY_CFG(_id, _offset, _shift, _width, _flags, _table, _ready)\ argument
528 [(_id)] = {\
537 #define DIV_CFG(_id, _offset, _shift, _width, _flags, _table)\ argument
538 DIVRDY_CFG(_id, _offset, _shift, _width, _flags, _table, DIV_NO_RDY)
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| H A D | clk-stm32mp21.c | 382 #define GATE_CFG(_id, _offset, _bit_idx, _offset_clr)\ argument
383 [(_id)] = {\
566 #define _MUX_CFG(_id, _offset, _shift, _width, _rdy)\ argument
567 [(_id)] = {\
611 #define _DIV_CFG(_id, _offset, _shift, _width, _flags, _table, _ready)\ argument
612 [(_id)] = {\
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| H A D | clk-stm32mp25.c | 372 #define GATE_CFG(_id, _offset, _bit_idx, _offset_clr)\ argument
373 [(_id)] = {\
601 #define _MUX_CFG(_id, _offset, _shift, _width, _rdy)\ argument
602 [(_id)] = {\
651 #define _DIV_CFG(_id, _offset, _shift, _width, _flags, _table, _ready)\ argument
652 [(_id)] = {\
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| /optee_os/core/arch/arm/plat-sam/ |
| H A D | scmi_server.c | 21 #define RESET_CELL(_scmi_id, _id, _name) \ argument
23 .reset_id = (_id), \
|