plat-stm32mp1: stm32mp1_pwr: fix compatible

Remove the unexpected comma in compatible name "st,stm32mp1,pwr-reg"

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Thomas

plat-stm32mp1: stm32mp1_pwr: fix compatible

Remove the unexpected comma in compatible name "st,stm32mp1,pwr-reg"

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Thomas Bourgoin <thomas.bourgoin@foss.st.com>
Reviewed-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: pwr: use IO_READ32_POLL_TIMEOUT()

Update stm32mp1_pwr driver to use IO_READ32_POLL_TIMEOUT() macro.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevall

plat-stm32mp1: pwr: use IO_READ32_POLL_TIMEOUT()

Update stm32mp1_pwr driver to use IO_READ32_POLL_TIMEOUT() macro.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: pwr: remove test on CFG_DRIVERS_REGULATOR

Remove tests on CFG_DRIVERS_REGULATOR value has the config switch
is always enabled on stm32mp1 platform.

Acked-by: Patrick Delaunay <patric

plat-stm32mp1: pwr: remove test on CFG_DRIVERS_REGULATOR

Remove tests on CFG_DRIVERS_REGULATOR value has the config switch
is always enabled on stm32mp1 platform.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: pwr: configure HSLV for fixed VDD supplied domain

Update PWR driver to configure High Speed Low Voltage mode for
fixed VDD supplied domain thanks to recently introduced SYSCFG HSLV
AP

plat-stm32mp1: pwr: configure HSLV for fixed VDD supplied domain

Update PWR driver to configure High Speed Low Voltage mode for
fixed VDD supplied domain thanks to recently introduced SYSCFG HSLV
API functions. This configuration must be appleid at boot time and
when resuming from a system low power state.

This configuration depends on VDD voltage level. It can protected by
a OTP bit (HW2 bit 13) described in the chip reference manual for when
VDD is supplied with a voltage below 2.5V. As stated in the chip
reference manual, enabling HSLV mode with a VDD voltage level above
2.7V may be destructive hence the driver panics in such case.

Acked-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Co-developed-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Pascal Paillet <p.paillet@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: stm32mp1_pwr: register regulators

Changes stm32mp1_pwr driver to be probed on from dt_driver framework
and register PWR regulators to the regulator framework.

Acked-by: Gatien Cheval

plat-stm32mp1: stm32mp1_pwr: register regulators

Changes stm32mp1_pwr driver to be probed on from dt_driver framework
and register PWR regulators to the regulator framework.

Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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plat-stm32mp1: fix timeout initializations

Fixes timeout initialization to ensure timeout monitoring starts
only once PWR regulator is enabled in stm32mp1_pwr driver and
once IO compensation is enab

plat-stm32mp1: fix timeout initializations

Fixes timeout initialization to ensure timeout monitoring starts
only once PWR regulator is enabled in stm32mp1_pwr driver and
once IO compensation is enabled in stm32mp1_syscfg driver.

Acked-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

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core_mmu: fix phys_to_virt() to check length

phys_to_virt() function without length parameter doesn`t
always have ability to find the correct mapping for
requested physical address. This is because

core_mmu: fix phys_to_virt() to check length

phys_to_virt() function without length parameter doesn`t
always have ability to find the correct mapping for
requested physical address. This is because physical
address can be mapped in the same time in different virtual
regions with different length. So the first found region
which contains the requested physical address possibly
doesn`t have enough mapped data. This is fixed by adding
the length parameter to phys_to_virt() function. Length
parameter can be set to 1 if caller knows that requested
(pa + len) doesn`t cross mapping granule boundary.

core_mmu_get_va() and io_pa_or_va() functions now are
take length parameter too as they based on phys_to_virt()
in case of MMU enabled.

Signed-off-by: Anton Rybakov <a.rybakov@omp.ru>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Etienne Carriere <etienne.carriere@linaro.org> (stm32mp1-157C_DK2)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabreauto)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6dlsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6qpsabreauto)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6sllevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ullevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx6ulzevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7dsabresd)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx7ulpevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mmevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mnevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mqevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8mpevk)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qmmek)
Tested-by: Clement Faure <clement.faure@nxp.com> (imx-mx8qxpmek)

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plat-stm32mp1: introduce PWR regulators

Introduce a voltage regulator driver for the voltage controllers
driven through PWR interface of stm32mp1 SoCs.

Signed-off-by: Etienne Carriere <etienne.carr

plat-stm32mp1: introduce PWR regulators

Introduce a voltage regulator driver for the voltage controllers
driven through PWR interface of stm32mp1 SoCs.

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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stm32mp1: use phys_to_virt_io_secure() where expected

This change updates platforms and drivers to use io_pa_or_va_secure()
when expecting a secure mapped address.

PWR, RCC, GIC, TAMP, BSEC, ETZPC,

stm32mp1: use phys_to_virt_io_secure() where expected

This change updates platforms and drivers to use io_pa_or_va_secure()
when expecting a secure mapped address.

PWR, RCC, GIC, TAMP, BSEC, ETZPC, I2C are always secure (when embedded).

RNG uses a secure or non-secure mapping according to its registration in
platform shared_resource driver.

GPIOs IO memory is always access though non-secure mapped virtual
addresses.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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stm32mp1: prefer vaddr_t to uintptr_t

Use vaddr_t and paddr_t instead of uintptr_t where applicable.

This change also simplifies some platform get-base-address functions
to use io_pa_or_va().

Sign

stm32mp1: prefer vaddr_t to uintptr_t

Use vaddr_t and paddr_t instead of uintptr_t where applicable.

This change also simplifies some platform get-base-address functions
to use io_pa_or_va().

Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Reviewed-by: Jerome Forissier <jerome.forissier@linaro.org>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

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stm32mp1: PWR support

PWR is a memory mapped SoC interface for power control. This change
maps and defines the interface for the stm32mp1 platform.

Signed-off-by: Etienne Carriere <etienne.carriere

stm32mp1: PWR support

PWR is a memory mapped SoC interface for power control. This change
maps and defines the interface for the stm32mp1 platform.

Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Acked-by: Jerome Forissier <jerome.forissier@linaro.org>

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