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Searched refs:train_set (Results 1 – 12 of 12) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/
H A Dcdn-dp-link-training.c18 u8 swing = (dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) >> in cdn_dp_set_signal_levels()
20 u8 pre_emphasis = (dp->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) in cdn_dp_set_signal_levels()
123 dp->train_set[i] = v | p; in cdn_dp_get_adjust_train()
153 if ((dp->train_set[lane] & DP_TRAIN_MAX_SWING_REACHED) == 0) in cdn_dp_link_max_vswing_reached()
166 dp->train_set, dp->link.num_lanes); in cdn_dp_update_link_train()
176 uint8_t buf[sizeof(dp->train_set) + 1]; in cdn_dp_set_link_train()
186 memcpy(buf + 1, dp->train_set, dp->link.num_lanes); in cdn_dp_set_link_train()
203 memset(dp->train_set, 0, sizeof(dp->train_set)); in cdn_dp_reset_link_train()
255 voltage = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in cdn_dp_link_training_clock_recovery()
264 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == in cdn_dp_link_training_clock_recovery()
H A Ddw-dp.c1490 struct drm_dp_link_train_set *train_set) in dw_dp_phy_update_vs_emph() argument
1497 vs = train_set->voltage_swing; in dw_dp_phy_update_vs_emph()
1498 pe = train_set->pre_emphasis; in dw_dp_phy_update_vs_emph()
1518 if (train_set->voltage_max_reached[i]) in dw_dp_phy_update_vs_emph()
1520 if (train_set->pre_max_reached[i]) in dw_dp_phy_update_vs_emph()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Datombios_dp.c202 u8 train_set[4]) in amdgpu_atombios_dp_get_adjust_train()
234 train_set[lane] = v | p; in amdgpu_atombios_dp_get_adjust_train()
493 u8 train_set[4]; member
505 0, dp_info->train_set[0]); /* sets all lanes at once */ in amdgpu_atombios_dp_update_vs_emph()
509 dp_info->train_set, dp_info->dp_lane_count); in amdgpu_atombios_dp_update_vs_emph()
603 memset(dp_info->train_set, 0, 4); in amdgpu_atombios_dp_link_train_cr()
627 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in amdgpu_atombios_dp_link_train_cr()
635 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in amdgpu_atombios_dp_link_train_cr()
644 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in amdgpu_atombios_dp_link_train_cr()
648 dp_info->train_set); in amdgpu_atombios_dp_link_train_cr()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/
H A Dintel_dp_link_training.c86 intel_dp->train_set[lane] = v | p; in intel_dp_get_adjust_train()
93 u8 buf[sizeof(intel_dp->train_set) + 1]; in intel_dp_set_link_train()
105 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); in intel_dp_set_link_train()
119 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); in intel_dp_reset_link_train()
132 intel_dp->train_set, intel_dp->lane_count); in intel_dp_update_link_train()
142 if ((intel_dp->train_set[lane] & in intel_dp_link_max_vswing_reached()
261 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in intel_dp_link_training_clock_recovery()
271 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == in intel_dp_link_training_clock_recovery()
H A Dintel_dp.c4176 u8 train_set = intel_dp->train_set[0]; in vlv_set_signal_levels() local
4178 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in vlv_set_signal_levels()
4181 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
4204 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
4223 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
4238 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_set_signal_levels()
4260 u8 train_set = intel_dp->train_set[0]; in chv_set_signal_levels() local
4262 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in chv_set_signal_levels()
4264 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in chv_set_signal_levels()
4287 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in chv_set_signal_levels()
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H A Dintel_display_types.h1303 u8 train_set[4]; member
H A Dintel_ddi.c2825 u8 train_set = intel_dp->train_set[0]; in intel_ddi_dp_level() local
2826 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | in intel_ddi_dp_level()
H A Dintel_display_debugfs.c1391 intel_dp->train_set[0]); in i915_displayport_test_data_show()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/radeon/
H A Datombios_dp.c258 u8 train_set[4]) in dp_get_adjust_train()
290 train_set[lane] = v | p; in dp_get_adjust_train()
545 u8 train_set[4]; member
557 0, dp_info->train_set[0]); /* sets all lanes at once */ in radeon_dp_update_vs_emph()
561 dp_info->train_set, dp_info->dp_lane_count); in radeon_dp_update_vs_emph()
672 memset(dp_info->train_set, 0, 4); in radeon_dp_link_train_cr()
696 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in radeon_dp_link_train_cr()
704 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in radeon_dp_link_train_cr()
713 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in radeon_dp_link_train_cr()
716 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); in radeon_dp_link_train_cr()
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/OK3568_Linux_fs/u-boot/drivers/video/rockchip/
H A Drk_edp.c44 u8 train_set[4]; member
422 u8 train_set[]) in edp_get_adjust_train() argument
459 train_set[lane] = v | p; in edp_get_adjust_train()
476 memset(edp->train_set, '\0', sizeof(edp->train_set)); in rk_edp_link_train_cr()
484 rk_edp_set_link_training(edp, edp->train_set); in rk_edp_link_train_cr()
486 edp->train_set, in rk_edp_link_train_cr()
505 if ((edp->train_set[i] & in rk_edp_link_train_cr()
514 if ((edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == in rk_edp_link_train_cr()
524 voltage = edp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in rk_edp_link_train_cr()
528 edp->train_set); in rk_edp_link_train_cr()
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/OK3568_Linux_fs/kernel/drivers/gpu/drm/xlnx/
H A Dzynqmp_dp.c320 u8 train_set[ZYNQMP_DP_MAX_LANES]; member
614 u8 *train_set = dp->train_set; in zynqmp_dp_adjust_train() local
636 train_set[i] = voltage | preemphasis; in zynqmp_dp_adjust_train()
654 ret = drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->train_set, in zynqmp_dp_update_vs_emph()
662 u8 train = dp->train_set[i]; in zynqmp_dp_update_vs_emph()
720 if (!(dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED)) in zynqmp_dp_link_train_cr()
725 if ((dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == vs) in zynqmp_dp_link_train_cr()
733 vs = dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in zynqmp_dp_link_train_cr()
863 memset(dp->train_set, 0, sizeof(dp->train_set)); in zynqmp_dp_train()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c271 uint8_t train_set[4]; member
1302 intel_dp->train_set[lane] = v | p; in cdv_intel_get_adjust_train()
1393 intel_dp->train_set, in cdv_intel_dplink_set_level()
1398 intel_dp->train_set[0], intel_dp->lane_count); in cdv_intel_dplink_set_level()
1498 memset(intel_dp->train_set, 0, 4); in cdv_intel_dp_start_link_train()
1510 intel_dp->train_set[0], in cdv_intel_dp_start_link_train()
1517 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]); in cdv_intel_dp_start_link_train()
1538 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in cdv_intel_dp_start_link_train()
1544 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in cdv_intel_dp_start_link_train()
1550 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in cdv_intel_dp_start_link_train()
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