| /OK3568_Linux_fs/kernel/arch/mips/ath79/ |
| H A D | clock.c | 93 static void __init ar71xx_clocks_init(void __iomem *pll_base) in ar71xx_clocks_init() argument
105 pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG); in ar71xx_clocks_init()
124 static void __init ar724x_clocks_init(void __iomem *pll_base) in ar724x_clocks_init() argument
131 pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG); in ar724x_clocks_init()
144 static void __init ar933x_clocks_init(void __iomem *pll_base) in ar933x_clocks_init() argument
165 clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG); in ar933x_clocks_init()
178 cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG); in ar933x_clocks_init()
232 static void __init ar934x_clocks_init(void __iomem *pll_base) in ar934x_clocks_init() argument
265 pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG); in ar934x_clocks_init()
292 pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG); in ar934x_clocks_init()
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| /OK3568_Linux_fs/kernel/drivers/clk/imx/ |
| H A D | clk-imx5.c | 283 void __iomem *pll_base; in mx50_clocks_init() local
286 pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K); in mx50_clocks_init()
287 WARN_ON(!pll_base); in mx50_clocks_init()
288 clk[IMX5_CLK_PLL1_SW] = imx_clk_pllv2("pll1_sw", "osc", pll_base); in mx50_clocks_init()
290 pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K); in mx50_clocks_init()
291 WARN_ON(!pll_base); in mx50_clocks_init()
292 clk[IMX5_CLK_PLL2_SW] = imx_clk_pllv2("pll2_sw", "osc", pll_base); in mx50_clocks_init()
294 pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K); in mx50_clocks_init()
295 WARN_ON(!pll_base); in mx50_clocks_init()
296 clk[IMX5_CLK_PLL3_SW] = imx_clk_pllv2("pll3_sw", "osc", pll_base); in mx50_clocks_init()
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-davinci/ |
| H A D | cpu.c | 61 unsigned int pll_base; in clk_get() local
69 pll_base = (unsigned int)davinci_pllc1_regs; in clk_get()
71 pll_base = (unsigned int)davinci_pllc0_regs; in clk_get()
79 pre_div = (readl(pll_base + PLLC_PREDIV) & in clk_get()
81 pllm = readl(pll_base + PLLC_PLLM) + 1; in clk_get()
89 post_div = (readl(pll_base + PLLC_POSTDIV) & in clk_get()
97 pll_out /= (readl(pll_base + sysdiv[id - 1]) & in clk_get()
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| /OK3568_Linux_fs/kernel/drivers/video/fbdev/omap2/omapfb/dss/ |
| H A D | video-pll.c | 134 void __iomem *pll_base, *clkctrl_base; in dss_video_pll_init() local
148 pll_base = devm_ioremap_resource(&pdev->dev, res); in dss_video_pll_init()
149 if (IS_ERR(pll_base)) { in dss_video_pll_init()
151 return ERR_CAST(pll_base); in dss_video_pll_init()
191 pll->base = pll_base; in dss_video_pll_init()
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| H A D | dsi.c | 294 void __iomem *pll_base; member
440 case DSI_PLL: base = dsi->pll_base; break; in dsi_write_reg()
456 case DSI_PLL: base = dsi->pll_base; break; in dsi_read_reg()
5226 pll->base = dsi->pll_base; in dsi_init_pll_data()
5351 dsi->pll_base = devm_ioremap(&dsidev->dev, res->start, in dsi_bind()
5353 if (!dsi->pll_base) { in dsi_bind()
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/omapdrm/dss/ |
| H A D | video-pll.c | 142 void __iomem *pll_base, *clkctrl_base; in dss_video_pll_init() local
150 pll_base = devm_ioremap_resource(&pdev->dev, res); in dss_video_pll_init()
151 if (IS_ERR(pll_base)) in dss_video_pll_init()
152 return ERR_CAST(pll_base); in dss_video_pll_init()
183 pll->base = pll_base; in dss_video_pll_init()
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| H A D | dsi.c | 323 void __iomem *pll_base; member
443 case DSI_PLL: base = dsi->pll_base; break; in dsi_write_reg()
457 case DSI_PLL: base = dsi->pll_base; break; in dsi_read_reg()
5029 pll->base = dsi->pll_base; in dsi_init_pll_data()
5309 dsi->pll_base = devm_ioremap_resource(dev, res); in dsi_probe()
5310 if (IS_ERR(dsi->pll_base)) in dsi_probe()
5311 return PTR_ERR(dsi->pll_base); in dsi_probe()
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/ |
| H A D | cpu.c | 180 if (readl(&pll->pll_base) & PLL_ENABLE_MASK) { in pllx_set_rate()
190 writel(reg, &pll->pll_base); in pllx_set_rate()
208 reg = readl(&pll->pll_base); in pllx_set_rate()
210 writel(reg, &pll->pll_base); in pllx_set_rate()
221 reg = readl(&pll->pll_base); in pllx_set_rate()
223 writel(reg, &pll->pll_base); in pllx_set_rate()
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| H A D | clock.c | 102 data = readl(&pll->pll_base); in clock_ll_read_pll()
154 writel(data, &pll->pll_base); in clock_start_pll()
157 writel(data, &simple_pll->pll_base); in clock_start_pll()
550 base = readl(&pll->pll_base); in clock_get_rate()
597 base_reg = readl(&pll->pll_base); in clock_set_rate()
616 if (base_reg != readl(&pll->pll_base)) in clock_set_rate()
624 writel(base_reg, &pll->pll_base); in clock_set_rate()
634 writel(base_reg, &pll->pll_base); in clock_set_rate()
638 writel(base_reg, &pll->pll_base); in clock_set_rate()
676 u32 reg = readl(&pll->pll_base); in clock_verify()
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| /OK3568_Linux_fs/kernel/drivers/clk/ |
| H A D | clk-bm1880.c | 63 void __iomem *pll_base; member
530 void __iomem *pll_base = data->pll_base; in bm1880_clk_register_plls() local
536 hw = bm1880_clk_register_pll(bm1880_clk, pll_base); in bm1880_clk_register_plls()
877 void __iomem *pll_base, *sys_base; in bm1880_clk_probe() local
883 pll_base = devm_ioremap_resource(&pdev->dev, res); in bm1880_clk_probe()
884 if (IS_ERR(pll_base)) in bm1880_clk_probe()
885 return PTR_ERR(pll_base); in bm1880_clk_probe()
903 clk_data->pll_base = pll_base; in bm1880_clk_probe()
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | warmboot_avp.c | 189 writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); in wb_start()
192 writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); in wb_start()
194 writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); in wb_start()
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| /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/display/msm/ |
| H A D | edp.txt | 9 * "pll_base"
33 "pll_base";
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| /OK3568_Linux_fs/kernel/drivers/clk/st/ |
| H A D | clkgen-pll.c | 693 void __iomem *pll_base; in clkgen_c32_pll_setup() local
703 pll_base = clkgen_get_register_base(np); in clkgen_c32_pll_setup()
704 if (!pll_base) in clkgen_c32_pll_setup()
709 clk = clkgen_pll_register(parent_name, data, pll_base, pll_flags, in clkgen_c32_pll_setup()
740 clk = clkgen_odf_register(pll_name, pll_base, data, odf_flags, in clkgen_c32_pll_setup()
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| /OK3568_Linux_fs/kernel/arch/arm/mach-tegra/ |
| H A D | sleep-tegra20.S | 46 .macro pll_enable, rd, r_car_base, pll_base argument
47 ldr \rd, [\r_car_base, #\pll_base]
50 streq \rd, [\r_car_base, #\pll_base]
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| H A D | sleep-tegra30.S | 90 .macro pll_enable, rd, r_car_base, pll_base, pll_misc
91 ldr \rd, [\r_car_base, #\pll_base]
94 streq \rd, [\r_car_base, #\pll_base]
107 .macro pll_locked, rd, r_car_base, pll_base argument
109 ldr \rd, [\r_car_base, #\pll_base]
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| /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra/ |
| H A D | clk_rst.h | 13 uint pll_base; /* the control register */ member
21 uint pll_base; /* the control register */ member
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra124/ |
| H A D | cpu.c | 55 reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); in enable_cpu_clocks()
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra114/ |
| H A D | cpu.c | 62 reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); in enable_cpu_clocks()
|