1*4882a593SmuzhiyunQualcomm Technologies Inc. adreno/snapdragon eDP output 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: 5*4882a593Smuzhiyun * "qcom,mdss-edp" 6*4882a593Smuzhiyun- reg: Physical base address and length of the registers of controller and PLL 7*4882a593Smuzhiyun- reg-names: The names of register regions. The following regions are required: 8*4882a593Smuzhiyun * "edp" 9*4882a593Smuzhiyun * "pll_base" 10*4882a593Smuzhiyun- interrupts: The interrupt signal from the eDP block. 11*4882a593Smuzhiyun- power-domains: Should be <&mmcc MDSS_GDSC>. 12*4882a593Smuzhiyun- clocks: device clocks 13*4882a593Smuzhiyun See Documentation/devicetree/bindings/clock/clock-bindings.txt for details. 14*4882a593Smuzhiyun- clock-names: the following clocks are required: 15*4882a593Smuzhiyun * "core" 16*4882a593Smuzhiyun * "iface" 17*4882a593Smuzhiyun * "mdp_core" 18*4882a593Smuzhiyun * "pixel" 19*4882a593Smuzhiyun * "link" 20*4882a593Smuzhiyun- #clock-cells: The value should be 1. 21*4882a593Smuzhiyun- vdda-supply: phandle to vdda regulator device node 22*4882a593Smuzhiyun- lvl-vdd-supply: phandle to regulator device node which is used to supply power 23*4882a593Smuzhiyun to HPD receiving chip 24*4882a593Smuzhiyun- panel-en-gpios: GPIO pin to supply power to panel. 25*4882a593Smuzhiyun- panel-hpd-gpios: GPIO pin used for eDP hpd. 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunExample: 29*4882a593Smuzhiyun mdss_edp: qcom,mdss_edp@fd923400 { 30*4882a593Smuzhiyun compatible = "qcom,mdss-edp"; 31*4882a593Smuzhiyun reg-names = 32*4882a593Smuzhiyun "edp", 33*4882a593Smuzhiyun "pll_base"; 34*4882a593Smuzhiyun reg = <0xfd923400 0x700>, 35*4882a593Smuzhiyun <0xfd923a00 0xd4>; 36*4882a593Smuzhiyun interrupt-parent = <&mdss_mdp>; 37*4882a593Smuzhiyun interrupts = <12 0>; 38*4882a593Smuzhiyun power-domains = <&mmcc MDSS_GDSC>; 39*4882a593Smuzhiyun clock-names = 40*4882a593Smuzhiyun "core", 41*4882a593Smuzhiyun "pixel", 42*4882a593Smuzhiyun "iface", 43*4882a593Smuzhiyun "link", 44*4882a593Smuzhiyun "mdp_core"; 45*4882a593Smuzhiyun clocks = 46*4882a593Smuzhiyun <&mmcc MDSS_EDPAUX_CLK>, 47*4882a593Smuzhiyun <&mmcc MDSS_EDPPIXEL_CLK>, 48*4882a593Smuzhiyun <&mmcc MDSS_AHB_CLK>, 49*4882a593Smuzhiyun <&mmcc MDSS_EDPLINK_CLK>, 50*4882a593Smuzhiyun <&mmcc MDSS_MDP_CLK>; 51*4882a593Smuzhiyun #clock-cells = <1>; 52*4882a593Smuzhiyun vdda-supply = <&pma8084_l12>; 53*4882a593Smuzhiyun lvl-vdd-supply = <&lvl_vreg>; 54*4882a593Smuzhiyun panel-en-gpios = <&tlmm 137 0>; 55*4882a593Smuzhiyun panel-hpd-gpios = <&tlmm 103 0>; 56*4882a593Smuzhiyun }; 57