Searched refs:pll5_cfg (Results 1 – 9 of 9) sorted by relevance
247 reg_val = readl(&ccm->pll5_cfg); in mctl_setup_dram_clock()289 writel(reg_val, &ccm->pll5_cfg); in mctl_setup_dram_clock()292 setbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_DDR_CLK); in mctl_setup_dram_clock()
118 div1 << CCM_PLL5_DIV1_SHIFT, &ccm->pll5_cfg); in clock_set_pll5()
211 uint32_t rval = readl(&ccm->pll5_cfg); in clock_get_pll5p()
208 CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg); in clock_set_pll5()
400 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); in mctl_sys_init()
376 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN); in mctl_sys_init()
25 u32 pll5_cfg; /* 0x20 pll5 ddr control */ member
23 u32 pll5_cfg; /* 0x20 pll5 control */ member