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Searched refs:pipe_bpp (Results 1 – 18 of 18) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/display/
H A Dintel_lvds.c288 if (pipe_config->dither && pipe_config->pipe_bpp == 18) in intel_pre_enable_lvds()
419 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { in intel_lvds_compute_config()
422 pipe_config->pipe_bpp, lvds_bpp); in intel_lvds_compute_config()
423 pipe_config->pipe_bpp = lvds_bpp; in intel_lvds_compute_config()
H A Dintel_dp_mst.c63 crtc_state->pipe_bpp = bpp; in intel_dp_mst_compute_link_config()
66 crtc_state->pipe_bpp, in intel_dp_mst_compute_link_config()
86 intel_link_compute_m_n(crtc_state->pipe_bpp, in intel_dp_mst_compute_link_config()
144 limits.max_bpp = min(pipe_config->pipe_bpp, 24); in intel_dp_mst_compute_config()
H A Dintel_hdmi.c949 static bool gcp_default_phase_possible(int pipe_bpp, in gcp_default_phase_possible() argument
954 switch (pipe_bpp) { in gcp_default_phase_possible()
1044 if (crtc_state->pipe_bpp > 24) in intel_hdmi_compute_gcp_infoframe()
1048 if (gcp_default_phase_possible(crtc_state->pipe_bpp, in intel_hdmi_compute_gcp_infoframe()
1810 if (crtc_state->pipe_bpp > 24) in intel_hdmi_prepare()
1983 if (pipe_config->pipe_bpp > 24 && in ibx_enable_hdmi()
2031 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
2042 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
2292 if (crtc_state->pipe_bpp < bpc * 3) in intel_hdmi_deep_color_possible()
2436 if (crtc_state->pipe_bpp > bpc * 3) in intel_hdmi_compute_clock()
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H A Dintel_dp.c2043 bpc = crtc_state->pipe_bpp / 3; in intel_dp_max_bpp()
2147 pipe_config->pipe_bpp = bpp; in intel_dp_compute_link_config_wide()
2243 int pipe_bpp; in intel_dp_dsc_compute_config() local
2259 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc); in intel_dp_dsc_compute_config()
2262 if (pipe_bpp < 8 * 3) { in intel_dp_dsc_compute_config()
2273 pipe_config->pipe_bpp = pipe_bpp; in intel_dp_dsc_compute_config()
2280 pipe_config->pipe_bpp); in intel_dp_dsc_compute_config()
2305 pipe_config->pipe_bpp); in intel_dp_dsc_compute_config()
2328 pipe_config->pipe_bpp, in intel_dp_dsc_compute_config()
2336 pipe_config->pipe_bpp, in intel_dp_dsc_compute_config()
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H A Dintel_ddi.c1552 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24) in ddi_dotclock_get()
1553 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp; in ddi_dotclock_get()
1600 switch (crtc_state->pipe_bpp) { in intel_ddi_set_dp_msa()
1614 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_set_dp_msa()
1677 switch (crtc_state->pipe_bpp) { in intel_ddi_transcoder_func_reg_val_get()
4341 pipe_config->pipe_bpp = 18; in intel_ddi_get_config()
4344 pipe_config->pipe_bpp = 24; in intel_ddi_get_config()
4347 pipe_config->pipe_bpp = 30; in intel_ddi_get_config()
4350 pipe_config->pipe_bpp = 36; in intel_ddi_get_config()
4440 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { in intel_ddi_get_config()
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H A Dicl_dsi.c1469 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); in gen11_dsi_get_config()
1488 if (crtc_state->pipe_bpp < 8 * 3) in gen11_dsi_dsc_compute_config()
1549 pipe_config->pipe_bpp = 24; in gen11_dsi_compute_config()
1551 pipe_config->pipe_bpp = 18; in gen11_dsi_compute_config()
H A Dintel_crt.c432 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { in hsw_crt_compute_config()
438 pipe_config->pipe_bpp = 24; in hsw_crt_compute_config()
H A Dvlv_dsi.c295 pipe_config->pipe_bpp = 24; in intel_dsi_compute_config()
297 pipe_config->pipe_bpp = 18; in intel_dsi_compute_config()
1107 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); in bxt_dsi_get_pipe_config()
H A Dintel_display.c7918 pipe_config->pipe_bpp); in ilk_fdi_compute_config()
7922 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, in ilk_fdi_compute_config()
7929 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { in ilk_fdi_compute_config()
7930 pipe_config->pipe_bpp -= 2*3; in ilk_fdi_compute_config()
7933 pipe_config->pipe_bpp); in ilk_fdi_compute_config()
7958 if (crtc_state->pipe_bpp > 24) in hsw_crtc_state_ips_capable()
8994 if (crtc_state->dither && crtc_state->pipe_bpp != 30) in i9xx_set_pipeconf()
8998 switch (crtc_state->pipe_bpp) { in i9xx_set_pipeconf()
9488 pipe_config->pipe_bpp = 18; in i9xx_get_pipe_config()
9491 pipe_config->pipe_bpp = 24; in i9xx_get_pipe_config()
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H A Dintel_audio.c275 if (crtc_state->pipe_bpp == 36) { in audio_config_hdmi_get_n()
278 } else if (crtc_state->pipe_bpp == 30) { in audio_config_hdmi_get_n()
H A Dintel_psr.c763 if (crtc_state->pipe_bpp > max_bpp) { in intel_psr2_config_valid()
766 crtc_state->pipe_bpp, max_bpp); in intel_psr2_config_valid()
H A Dintel_vdsc.c400 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; in intel_dsc_compute_params()
H A Dintel_display_types.h922 int pipe_bpp; member
H A Dintel_bios.c2502 crtc_state->pipe_bpp = bpc * 3; in fill_dsc()
2504 crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp, in fill_dsc()
H A Dintel_tv.c1204 pipe_config->pipe_bpp = 8*3; in intel_tv_compute_config()
H A Dintel_display_debugfs.c867 yesno(crtc_state->dither), crtc_state->pipe_bpp); in intel_crtc_info()
H A Dintel_panel.c448 if (INTEL_GEN(dev_priv) < 4 && crtc_state->pipe_bpp == 18) in intel_gmch_panel_fitting()
H A Dintel_sdvo.c1314 pipe_config->pipe_bpp = 8*3; in intel_sdvo_compute_config()