Home
last modified time | relevance | path

Searched refs:phy_update_bits (Results 1 – 6 of 6) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/video/drm/
H A Dinno_video_combo_phy.c327 static inline void phy_update_bits(struct inno_video_phy *inno, in phy_update_bits() function
401 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_2_5GHz_pll_enable()
403 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_2_5GHz_pll_enable()
405 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, in inno_mipi_dphy_max_2_5GHz_pll_enable()
407 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08, in inno_mipi_dphy_max_2_5GHz_pll_enable()
409 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b, in inno_mipi_dphy_max_2_5GHz_pll_enable()
412 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_mipi_dphy_max_2_5GHz_pll_enable()
420 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_1GHz_pll_enable()
422 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_1GHz_pll_enable()
424 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, in inno_mipi_dphy_max_1GHz_pll_enable()
[all …]
H A Dsamsung_mipi_dcphy.c1211 static inline void phy_update_bits(struct samsung_mipi_dcphy *samsung, in phy_update_bits() function
1277 phy_update_bits(samsung, BIAS_CON4, I_MUX_SEL_MASK, I_MUX_SEL(2)); in samsung_mipi_dcphy_bias_block_enable()
1286 phy_update_bits(samsung, PLL_CON0, S_MASK | P_MASK, in samsung_mipi_dcphy_pll_configure()
1301 phy_update_bits(samsung, PLL_CON2, M_MASK, M(samsung->pll.fbdiv)); in samsung_mipi_dcphy_pll_configure()
1306 phy_update_bits(samsung, PLL_CON4, SSCG_EN, SSCG_EN); in samsung_mipi_dcphy_pll_configure()
1425 phy_update_bits(samsung, PLL_CON0, PLL_EN, PLL_EN); in samsung_mipi_dcphy_pll_enable()
1435 phy_update_bits(samsung, PLL_CON0, PLL_EN, 0); in samsung_mipi_dcphy_pll_disable()
1441 phy_update_bits(samsung, DPHY_MC_GNR_CON0, PHY_ENABLE, PHY_ENABLE); in samsung_mipi_dphy_lane_enable()
1446 phy_update_bits(samsung, DPHY_MD3_GNR_CON0, in samsung_mipi_dphy_lane_enable()
1451 phy_update_bits(samsung, COMBO_MD2_GNR_CON0, in samsung_mipi_dphy_lane_enable()
[all …]
H A Dinno_video_phy.c94 static inline void phy_update_bits(struct inno_video_phy *inno, in phy_update_bits() function
146 phy_update_bits(inno, 0x0030, DISABLE_PLL, 0); in inno_video_phy_power_on()
154 phy_update_bits(inno, 0x0084, ENABLE_TX, ENABLE_TX); in inno_video_phy_power_on()
163 phy_update_bits(inno, 0x0084, ENABLE_TX, 0); in inno_video_phy_power_off()
164 phy_update_bits(inno, 0x0030, DISABLE_PLL, DISABLE_PLL); in inno_video_phy_power_off()
/OK3568_Linux_fs/kernel/drivers/phy/rockchip/
H A Dphy-rockchip-inno-dsidphy.c306 static void phy_update_bits(struct inno_dsidphy *inno, in phy_update_bits() function
423 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_2_5GHz_pll_enable()
425 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_2_5GHz_pll_enable()
427 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, in inno_mipi_dphy_max_2_5GHz_pll_enable()
429 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08, in inno_mipi_dphy_max_2_5GHz_pll_enable()
431 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b, in inno_mipi_dphy_max_2_5GHz_pll_enable()
434 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_mipi_dphy_max_2_5GHz_pll_enable()
442 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_1GHz_pll_enable()
444 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_mipi_dphy_max_1GHz_pll_enable()
446 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, in inno_mipi_dphy_max_1GHz_pll_enable()
[all …]
H A Dphy-rockchip-inno-video-combo-phy.c235 static void phy_update_bits(struct inno_video_phy *inno, in phy_update_bits() function
315 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, in inno_video_phy_mipi_mode_enable()
318 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_video_phy_mipi_mode_enable()
320 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, in inno_video_phy_mipi_mode_enable()
322 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, in inno_video_phy_mipi_mode_enable()
325 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_video_phy_mipi_mode_enable()
329 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_video_phy_mipi_mode_enable()
332 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_video_phy_mipi_mode_enable()
335 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00, in inno_video_phy_mipi_mode_enable()
338 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00, in inno_video_phy_mipi_mode_enable()
[all …]
H A Dphy-rockchip-inno-usb2.c426 static inline void phy_update_bits(void __iomem *reg, u32 mask, u32 val) in phy_update_bits() function
2743 phy_update_bits(rphy->phy_base + 0x30, GENMASK(6, 4), (0x00 << 4)); in rk3528_usb2phy_tuning()
2746 phy_update_bits(rphy->phy_base + 0x430, GENMASK(6, 4), (0x00 << 4)); in rk3528_usb2phy_tuning()
2749 phy_update_bits(rphy->phy_base + 0x94, GENMASK(6, 3), (0x03 << 3)); in rk3528_usb2phy_tuning()
2766 phy_update_bits(rphy->phy_base, GENMASK(2, 0), 0x04); in rk3562_usb2phy_tuning()
2767 phy_update_bits(rphy->phy_base + 0x0400, GENMASK(2, 0), 0x04); in rk3562_usb2phy_tuning()
2770 phy_update_bits(rphy->phy_base + 0x0030, GENMASK(6, 4), (0x05 << 4)); in rk3562_usb2phy_tuning()
2771 phy_update_bits(rphy->phy_base + 0x0430, GENMASK(6, 4), (0x05 << 4)); in rk3562_usb2phy_tuning()
2793 phy_update_bits(rphy->phy_base, GENMASK(2, 0), 0x04); in rk3568_usb2phy_tuning()
2796 phy_update_bits(rphy->phy_base + 0x0400, GENMASK(2, 0), 0x04); in rk3568_usb2phy_tuning()
[all …]