306 static void phy_update_bits(struct inno_dsidphy *inno,  in phy_update_bits()  function
423 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,  in inno_mipi_dphy_max_2_5GHz_pll_enable()
425 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,  in inno_mipi_dphy_max_2_5GHz_pll_enable()
427 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,  in inno_mipi_dphy_max_2_5GHz_pll_enable()
429 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,  in inno_mipi_dphy_max_2_5GHz_pll_enable()
431 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b,  in inno_mipi_dphy_max_2_5GHz_pll_enable()
434 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,  in inno_mipi_dphy_max_2_5GHz_pll_enable()
442 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,  in inno_mipi_dphy_max_1GHz_pll_enable()
444 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,  in inno_mipi_dphy_max_1GHz_pll_enable()
446 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,  in inno_mipi_dphy_max_1GHz_pll_enable()
449 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,  in inno_mipi_dphy_max_1GHz_pll_enable()
457 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,  in inno_mipi_dphy_reset()
460 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,  in inno_mipi_dphy_reset()
463 	phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,  in inno_mipi_dphy_reset()
466 	phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,  in inno_mipi_dphy_reset()
545 		phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK,  in inno_mipi_dphy_timing_init()
547 		phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,  in inno_mipi_dphy_timing_init()
551 			phy_update_bits(inno, i, 0x06, T_HS_ZERO_CNT_HI_MASK,  in inno_mipi_dphy_timing_init()
554 		phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_LO_MASK,  in inno_mipi_dphy_timing_init()
556 		phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,  in inno_mipi_dphy_timing_init()
560 			phy_update_bits(inno, i, 0x11, T_HS_EXIT_CNT_HI_MASK,  in inno_mipi_dphy_timing_init()
563 		phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_LO_MASK,  in inno_mipi_dphy_timing_init()
567 			phy_update_bits(inno, i, 0x10, T_CLK_POST_HI_MASK,  in inno_mipi_dphy_timing_init()
570 		phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_LO_MASK,  in inno_mipi_dphy_timing_init()
572 		phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,  in inno_mipi_dphy_timing_init()
574 		phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,  in inno_mipi_dphy_timing_init()
576 		phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK,  in inno_mipi_dphy_timing_init()
578 		phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK,  in inno_mipi_dphy_timing_init()
580 		phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK,  in inno_mipi_dphy_timing_init()
582 		phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK,  in inno_mipi_dphy_timing_init()
607 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, val);  in inno_mipi_dphy_lane_enable()
613 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,  in inno_dsidphy_mipi_mode_enable()
618 		phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x01,  in inno_dsidphy_mipi_mode_enable()
638 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,  in inno_dsidphy_lvds_mode_enable()
644 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,  in inno_dsidphy_lvds_mode_enable()
648 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,  in inno_dsidphy_lvds_mode_enable()
653 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,  in inno_dsidphy_lvds_mode_enable()
656 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,  in inno_dsidphy_lvds_mode_enable()
658 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,  in inno_dsidphy_lvds_mode_enable()
660 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,  in inno_dsidphy_lvds_mode_enable()
662 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc);  in inno_dsidphy_lvds_mode_enable()
664 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,  in inno_dsidphy_lvds_mode_enable()
671 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1e,  in inno_dsidphy_lvds_mode_enable()
675 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,  in inno_dsidphy_lvds_mode_enable()
679 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,  in inno_dsidphy_lvds_mode_enable()
688 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,  in inno_dsidphy_phy_ttl_mode_enable()
692 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,  in inno_dsidphy_phy_ttl_mode_enable()
697 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,  in inno_dsidphy_phy_ttl_mode_enable()
701 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,  in inno_dsidphy_phy_ttl_mode_enable()
705 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,  in inno_dsidphy_phy_ttl_mode_enable()
723 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,  in inno_dsidphy_power_on()
726 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,  in inno_dsidphy_power_on()
747 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0);  in inno_dsidphy_power_off()
748 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,  in inno_dsidphy_power_off()
751 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,  in inno_dsidphy_power_off()
753 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,  in inno_dsidphy_power_off()
756 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0);  in inno_dsidphy_power_off()
757 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,  in inno_dsidphy_power_off()
760 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,  in inno_dsidphy_power_off()