| /OK3568_Linux_fs/kernel/drivers/phy/rockchip/ |
| H A D | phy-rockchip-inno-mipi-dphy.c | 275 static void inno_update_bits(struct inno_mipi_dphy *inno, u8 first, u8 second, in inno_update_bits() function
286 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_mipi_dphy_reset()
289 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x01, in inno_mipi_dphy_reset()
292 inno_update_bits(inno, REGISTER_PART_DIGITAL, 0x00, in inno_mipi_dphy_reset()
295 inno_update_bits(inno, REGISTER_PART_DIGITAL, 0x00, in inno_mipi_dphy_reset()
301 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00, in inno_mipi_dphy_power_work_enable()
307 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00, in inno_mipi_dphy_power_work_disable()
313 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00, in inno_mipi_dphy_bandgap_power_enable()
319 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00, in inno_mipi_dphy_bandgap_power_disable()
343 inno_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, val); in inno_mipi_dphy_lane_enable()
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| H A D | phy-rockchip-inno-hdmi-phy.c | 390 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg, in inno_update_bits() function
459 inno_update_bits(inno, 0x02, 1, 0); in inno_hdmi_phy_irq()
464 inno_update_bits(inno, 0x02, 1, 1); in inno_hdmi_phy_irq()
555 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, in inno_hdmi_phy_clk_prepare()
558 inno_update_bits(inno, 0xa0, 1, 0); in inno_hdmi_phy_clk_prepare()
568 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, in inno_hdmi_phy_clk_unprepare()
571 inno_update_bits(inno, 0xa0, 1, 1); in inno_hdmi_phy_clk_unprepare()
721 inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_DISABLE); in inno_hdmi_phy_rk3228_power_on()
724 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN); in inno_hdmi_phy_rk3228_power_on()
725 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN); in inno_hdmi_phy_rk3228_power_on()
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| H A D | phy-rockchip-inno-hdmi.c | 396 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg, in inno_update_bits() function
450 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, 0); in inno_hdmi_phy_rk3328_irq()
452 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, RK3328_PDATA_EN); in inno_hdmi_phy_rk3328_irq()
553 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, 0); in inno_hdmi_phy_rk3228_clk_prepare()
561 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, in inno_hdmi_phy_rk3228_clk_unprepare()
636 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, in inno_hdmi_phy_rk3228_clk_set_rate()
639 inno_update_bits(inno, 0xe2, RK3228_PRE_PLL_FB_DIV_8_MASK | in inno_hdmi_phy_rk3228_clk_set_rate()
646 inno_update_bits(inno, 0xe4, RK3228_PRE_PLL_PCLK_DIV_B_MASK | in inno_hdmi_phy_rk3228_clk_set_rate()
650 inno_update_bits(inno, 0xe5, RK3228_PRE_PLL_PCLK_DIV_C_MASK | in inno_hdmi_phy_rk3228_clk_set_rate()
654 inno_update_bits(inno, 0xe6, RK3228_PRE_PLL_TMDSCLK_DIV_C_MASK | in inno_hdmi_phy_rk3228_clk_set_rate()
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| /OK3568_Linux_fs/u-boot/drivers/video/drm/ |
| H A D | inno_mipi_phy.c | 265 static inline void inno_update_bits(struct inno_mipi_dphy *inno, u32 reg, in inno_update_bits() function
313 inno_update_bits(inno, base + T_HS_PREPARE_OFFSET, m, v); in inno_mipi_dphy_timing_update()
317 inno_update_bits(inno, base + T_HS_ZERO_OFFSET, m, v); in inno_mipi_dphy_timing_update()
321 inno_update_bits(inno, base + T_HS_TRAIL_OFFSET, m, v); in inno_mipi_dphy_timing_update()
325 inno_update_bits(inno, base + T_HS_EXIT_OFFSET, m, v); in inno_mipi_dphy_timing_update()
330 inno_update_bits(inno, base + T_CLK_POST_OFFSET, m, v); in inno_mipi_dphy_timing_update()
334 inno_update_bits(inno, base + T_CLK_PRE_OFFSET, m, v); in inno_mipi_dphy_timing_update()
339 inno_update_bits(inno, base + T_WAKUP_H_OFFSET, m, v); in inno_mipi_dphy_timing_update()
343 inno_update_bits(inno, base + T_WAKUP_L_OFFSET, m, v); in inno_mipi_dphy_timing_update()
347 inno_update_bits(inno, base + T_LPX_OFFSET, m, v); in inno_mipi_dphy_timing_update()
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| H A D | rockchip-inno-hdmi-phy.c | 359 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg, in inno_update_bits() function
522 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, in inno_hdmi_phy_clk_prepare()
525 inno_update_bits(inno, 0xa0, 1, 0); in inno_hdmi_phy_clk_prepare()
564 inno_update_bits(inno, 0x01, m, v); in inno_hdmi_phy_rk3228_init()
565 inno_update_bits(inno, 0x02, BYPASS_PDATA_EN_MASK, BYPASS_PDATA_EN); in inno_hdmi_phy_rk3228_init()
568 inno_update_bits(inno, 0xaa, POST_PLL_CTRL_MASK, POST_PLL_CTRL_MANUAL); in inno_hdmi_phy_rk3228_init()
580 inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_DISABLE); in inno_hdmi_phy_rk3228_power_on()
583 inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN); in inno_hdmi_phy_rk3228_power_on()
584 inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN); in inno_hdmi_phy_rk3228_power_on()
589 inno_update_bits(inno, 0xe9, m, v); in inno_hdmi_phy_rk3228_power_on()
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