359 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg,  in inno_update_bits()  function
522 		inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK,  in inno_hdmi_phy_clk_prepare()
525 		inno_update_bits(inno, 0xa0, 1, 0);  in inno_hdmi_phy_clk_prepare()
564 	inno_update_bits(inno, 0x01, m, v);  in inno_hdmi_phy_rk3228_init()
565 	inno_update_bits(inno, 0x02, BYPASS_PDATA_EN_MASK, BYPASS_PDATA_EN);  in inno_hdmi_phy_rk3228_init()
568 	inno_update_bits(inno, 0xaa, POST_PLL_CTRL_MASK, POST_PLL_CTRL_MANUAL);  in inno_hdmi_phy_rk3228_init()
580 	inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_DISABLE);  in inno_hdmi_phy_rk3228_power_on()
583 	inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN);  in inno_hdmi_phy_rk3228_power_on()
584 	inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN);  in inno_hdmi_phy_rk3228_power_on()
589 	inno_update_bits(inno, 0xe9, m, v);  in inno_hdmi_phy_rk3228_power_on()
593 	inno_update_bits(inno, 0xeb, m, v);  in inno_hdmi_phy_rk3228_power_on()
600 		inno_update_bits(inno, 0xe9, m, v);  in inno_hdmi_phy_rk3228_power_on()
605 		inno_update_bits(inno, 0xe9, m, v);  in inno_hdmi_phy_rk3228_power_on()
609 		inno_update_bits(inno, 0xeb, m, v);  in inno_hdmi_phy_rk3228_power_on()
616 	inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_UP);  in inno_hdmi_phy_rk3228_power_on()
617 	inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP);  in inno_hdmi_phy_rk3228_power_on()
620 	inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_ENABLE);  in inno_hdmi_phy_rk3228_power_on()
623 	inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_ENABLE);  in inno_hdmi_phy_rk3228_power_on()
641 	inno_update_bits(inno, 0x02, PDATAEN_MASK, PDATAEN_ENABLE);  in inno_hdmi_phy_rk3228_power_on()
648 	inno_update_bits(inno, 0xe1, TMDS_DRIVER_MASK, TMDS_DRIVER_DISABLE);  in inno_hdmi_phy_rk3228_power_off()
651 	inno_update_bits(inno, 0xe1, BANDGAP_MASK, BANDGAP_DISABLE);  in inno_hdmi_phy_rk3228_power_off()
654 	inno_update_bits(inno, 0xe0, POST_PLL_POWER_MASK, POST_PLL_POWER_DOWN);  in inno_hdmi_phy_rk3228_power_off()
665 	inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_DOWN);  in inno_hdmi_phy_rk3228_pre_pll_update()
670 	inno_update_bits(inno, 0xe2, m, v);  in inno_hdmi_phy_rk3228_pre_pll_update()
677 	inno_update_bits(inno, 0xe4, m, v);  in inno_hdmi_phy_rk3228_pre_pll_update()
682 	inno_update_bits(inno, 0xe5, m, v);  in inno_hdmi_phy_rk3228_pre_pll_update()
689 	inno_update_bits(inno, 0xe6, m, v);  in inno_hdmi_phy_rk3228_pre_pll_update()
692 	inno_update_bits(inno, 0xe0, PRE_PLL_POWER_MASK, PRE_PLL_POWER_UP);  in inno_hdmi_phy_rk3228_pre_pll_update()
727 	inno_update_bits(inno, 0x02, 1, 0);  in inno_hdmi_phy_rk3328_power_on()
729 	inno_update_bits(inno, 0xaa, 1, 1);  in inno_hdmi_phy_rk3328_power_on()
786 	inno_update_bits(inno, 0xaa, 1, 0);  in inno_hdmi_phy_rk3328_power_on()
788 	inno_update_bits(inno, 0xb0, 4, 4);  in inno_hdmi_phy_rk3328_power_on()
804 	inno_update_bits(inno, 0x02, 1, 1);  in inno_hdmi_phy_rk3328_power_on()
814 	inno_update_bits(inno, 0xb0, 4, 0);  in inno_hdmi_phy_rk3328_power_off()
816 	inno_update_bits(inno, 0xaa, 1, 1);  in inno_hdmi_phy_rk3328_power_off()
826 	inno_update_bits(inno, 0xa0, 1, 1);  in inno_hdmi_phy_rk3328_pre_pll_update()
828 	inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1);  in inno_hdmi_phy_rk3328_pre_pll_update()
861 	inno_update_bits(inno, 0xa0, 1, 0);  in inno_hdmi_phy_rk3328_pre_pll_update()
922 	inno_update_bits(inno, 0xaa, 1, 0);  in inno_hdmi_phy_rk3528_power_on()
939 	inno_update_bits(inno, 0xad, BIT(4), val);  in inno_hdmi_phy_rk3528_power_on()
1004 	inno_update_bits(inno, 0x02, 1, 0);  in inno_hdmi_phy_rk3528_power_on()
1005 	inno_update_bits(inno, 0x02, 1, 1);  in inno_hdmi_phy_rk3528_power_on()
1020 	inno_update_bits(inno, 0xb0, 4, 0);  in inno_hdmi_phy_rk3528_power_off()
1022 	inno_update_bits(inno, 0xaa, 1, 1);  in inno_hdmi_phy_rk3528_power_off()
1044 	inno_update_bits(inno, 0xb0, 4, 4);  in inno_hdmi_phy_rk3528_pre_pll_update()
1048 	inno_update_bits(inno, 0xa0, 1, 0);  in inno_hdmi_phy_rk3528_pre_pll_update()
1050 	inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1);  in inno_hdmi_phy_rk3528_pre_pll_update()