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Searched refs:effective_cs (Results 1 – 7 of 7) sorted by relevance

/OK3568_Linux_fs/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_pbs.c77 (effective_cs * CS_REGISTER_ADDR_OFFSET)) : in ddr3_tip_pbs()
79 (effective_cs * CS_REGISTER_ADDR_OFFSET)); in ddr3_tip_pbs()
192 (0x54 + effective_cs * 0x10) : in ddr3_tip_pbs()
193 (0x14 + effective_cs * 0x10); in ddr3_tip_pbs()
199 (0x55 + effective_cs * 0x10) : in ddr3_tip_pbs()
200 (0x15 + effective_cs * 0x10); in ddr3_tip_pbs()
252 (0x54 + effective_cs * 0x10) : in ddr3_tip_pbs()
253 (0x14 + effective_cs * 0x10); in ddr3_tip_pbs()
262 (0x55 + effective_cs * 0x10) : in ddr3_tip_pbs()
263 (0x15 + effective_cs * 0x10); in ddr3_tip_pbs()
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H A Dddr3_training_leveling.c151 for (effective_cs = 0; effective_cs < NUM_OF_CS; effective_cs++) in ddr3_tip_dynamic_read_leveling()
154 rl_values[effective_cs][bus_num][if_id] = 0; in ddr3_tip_dynamic_read_leveling()
156 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_dynamic_read_leveling()
192 effective_cs, STRESS_NONE, DURATION_SINGLE)); in ddr3_tip_dynamic_read_leveling()
213 (0x301b01 | effective_cs << 2), 0x3c3fef)); in ddr3_tip_dynamic_read_leveling()
350 rl_values[effective_cs][bus_num] in ddr3_tip_dynamic_read_leveling()
390 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_dynamic_read_leveling()
399 data = rl_values[effective_cs][bus_num][if_id]; in ddr3_tip_dynamic_read_leveling()
408 ((effective_cs == in ddr3_tip_dynamic_read_leveling()
414 effective_cs = 0; in ddr3_tip_dynamic_read_leveling()
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H A Dddr3_training.c70 u32 effective_cs = 0; variable
1258 ddr3_tip_calc_cs_mask(dev_num, if_id, effective_cs, in ddr3_tip_freq_set()
1779 if (cs_bitmask != effective_cs) { in ddr3_tip_write_cs_result()
1785 CS_REG_VALUE(effective_cs), in ddr3_tip_write_cs_result()
1892 CS_REG_VALUE(effective_cs), in ddr3_tip_ddr3_reset_phy_regs()
1897 RL_PHY_REG + CS_REG_VALUE(effective_cs), in ddr3_tip_ddr3_reset_phy_regs()
1903 CS_REG_VALUE(effective_cs), phy_reg3_val)); in ddr3_tip_ddr3_reset_phy_regs()
1908 CS_REG_VALUE(effective_cs), phy_reg3_val)); in ddr3_tip_ddr3_reset_phy_regs()
1973 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { in ddr3_tip_ddr3_training_main_flow()
1977 effective_cs = 0; in ddr3_tip_ddr3_training_main_flow()
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H A Dddr3_training_ip_engine.c222 (0x3 | (effective_cs << 26)), 0xc000003)); in ddr3_tip_ip_training()
246 delay_between_burst, rd_mode, effective_cs, STRESS_NONE, in ddr3_tip_ip_training()
299 effective_cs * CALIBRATED_OBJECTS_REG_ADDR_OFFSET; in ddr3_tip_ip_training()
303 effective_cs * CALIBRATED_OBJECTS_REG_ADDR_OFFSET; in ddr3_tip_ip_training()
314 reg_data = 1 + effective_cs * CS_REGISTER_ADDR_OFFSET; in ddr3_tip_ip_training()
318 reg_data = 3 + effective_cs * CS_REGISTER_ADDR_OFFSET; in ddr3_tip_ip_training()
814 (effective_cs << 26); in ddr3_tip_load_pattern_to_mem()
821 ODPG_DATA_CONTROL_REG, (0x1 | (effective_cs << 26)), in ddr3_tip_load_pattern_to_mem()
1192 (effective_cs * in ddr3_tip_load_phy_values()
1201 (effective_cs * in ddr3_tip_load_phy_values()
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H A Dddr3_init.h251 extern u32 effective_cs;
266 extern u32 effective_cs;
276 extern u32 effective_cs;
280 extern u32 effective_cs;
H A Dddr3_training_centralization.c98 reg_phy_off = WRITE_CENTRALIZATION_PHY_REG + (effective_cs * 4); in ddr3_tip_centralization()
102 reg_phy_off = READ_CENTRALIZATION_PHY_REG + (effective_cs * 4); in ddr3_tip_centralization()
193 effective_cs, pattern_id, in ddr3_tip_centralization()
445 effective_cs, &reg); in ddr3_tip_centralization()
459 effective_cs, reg)); in ddr3_tip_centralization()
H A Dddr3_training_leveling.h13 int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,