1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) Marvell International Ltd. and its affiliates 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef _DDR3_TRAINING_LEVELING_H_ 8*4882a593Smuzhiyun #define _DDR3_TRAINING_LEVELING_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define MAX_DQ_READ_LEVELING_DELAY 15 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun int ddr3_tip_print_wl_supp_result(u32 dev_num); 13*4882a593Smuzhiyun int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs, 14*4882a593Smuzhiyun u32 *cs_mask); 15*4882a593Smuzhiyun u32 hws_ddr3_tip_max_cs_get(void); 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #endif /* _DDR3_TRAINING_LEVELING_H_ */ 18