| /OK3568_Linux_fs/u-boot/arch/arm/mach-uniphier/clk/ |
| H A D | pll-base-ld20.c | 32 unsigned int ssc_rate, unsigned int divn) in uniphier_ld20_sscpll_init() argument
44 tmp |= (487 * freq * ssc_rate / divn / 512) & in uniphier_ld20_sscpll_init()
50 tmp |= (41859 * freq / divn) & SC_PLLCTRL2_SSC_JK_MASK; in uniphier_ld20_sscpll_init()
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| H A D | pll.h | 16 unsigned int ssc_rate, unsigned int divn);
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/ |
| H A D | cpu.c | 171 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, in pllx_set_rate() argument
189 reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift); in pllx_set_rate()
203 if (divn > 600) in pllx_set_rate()
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| H A D | clock.c | 90 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, in clock_ll_read_pll() argument
104 *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask; in clock_ll_read_pll()
114 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, in clock_start_pll() argument
148 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift); in clock_start_pll()
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | warmboot.c | 154 u32 divm, divn, divp, cpcon, lfcon; in warmboot_save_sdram_params() local
156 if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp, in warmboot_save_sdram_params()
160 scratch2.pllm_base_divn = divn; in warmboot_save_sdram_params()
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| H A D | warmboot_avp.c | 169 pllx_base.divn = scratch3.pllx_base_divn; in wb_start()
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| /OK3568_Linux_fs/u-boot/arch/arm/include/asm/arch-tegra/ |
| H A D | clock.h | 62 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
89 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
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| H A D | warmboot.h | 74 u32 divn:10; member
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| /OK3568_Linux_fs/u-boot/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 1067 u32 divm, divn, divp, cpcon; in clock_set_display_rate() local
1094 divn = vco / cf; in clock_set_display_rate()
1095 if (divn >= max_n) in clock_set_display_rate()
1098 diff = vco - divn * cf; in clock_set_display_rate()
1099 if (divn + 1 < max_n && diff > cf / 2) { in clock_set_display_rate()
1100 divn++; in clock_set_display_rate()
1109 best_n = divn; in clock_set_display_rate()
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| /OK3568_Linux_fs/kernel/drivers/media/dvb-frontends/ |
| H A D | si2165.c | 206 u8 divn = 56; /* 1..63 */ in si2165_init_pll() local
217 divn = 56; in si2165_init_pll()
222 divn = 19; in si2165_init_pll()
237 divn = 1624000000u * divr / (ref_freq_hz * 2u * divp); in si2165_init_pll()
243 * 2u * divn * divp; in si2165_init_pll()
250 buf[2] = (divn & 0x3f) | ((divp == 1) ? 0x40 : 0x00) | 0x80; in si2165_init_pll()
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| /OK3568_Linux_fs/kernel/drivers/clk/ |
| H A D | clk-stm32mp1.c | 826 u32 frac, divm, divn; in pll_recalc_rate() local
832 divn = ((reg >> DIVN_SHIFT) & DIVN_MASK) + 1; in pll_recalc_rate()
833 rate = (u64)parent_rate * divn; in pll_recalc_rate()
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| /OK3568_Linux_fs/kernel/drivers/clk/tegra/ |
| H A D | clk-pll.c | 1018 u32 divn = 0, divm = 0, divp = 0; in clk_plle_recalc_rate() local
1022 divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll)); in clk_plle_recalc_rate()
1026 rate *= divn; in clk_plle_recalc_rate()
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